LPC824 UART slave sync mode ignore first two clock's

[lpcware]

Content originally posted in LPCWare by s20550 on Wed Nov 18 01:34:15 MST 2015
LPC824 UART(RX and TX) in slave sync mode ignore first two clock's. 
Master mode work fine.
Connect LPC824 master sync <-> slave sync impossible!

[lpcware]

Content originally posted in LPCWare by s20550 on Wed Nov 18 02:20:16 MST 2015
[img]https://www.lpcware.com/system/files/WA000001.jpg[/img]
yellow - master sclk(request)
blue - slave tx(answer)

my sys config

sysclk - pll from irc witch msel = 5 psel = 2.  ->  main clock = 60Mhz.
SYSAHBCLKDIV = 2 -> system clock = 30Mhz.

my usart config

USART.CFG = ENABLE | DATALEN(1)  | SYNCEN | CLKPOL;
USART.CTL = 0;
USART.BRG = 0;