LPC77x_8x timer question

[lpcware]

Content originally posted in LPCWare by williamjsell on Tue Sep 24 13:34:28 MST 2013
What I would like to do is use a single timer to generate multiple timing events.  This does not seem possible, but I shall ask to see I am missing something.  There are 4 match registers in the timer, but they are matched to a single timer counter.  This seems to restrict usefulness.  If I setup the first match reg to have x counts and the 2nd to have y counts, then I am faced with several options: reset the TC when the first match hits, but this means the 2nd match will never hit.  reset the TC on the second match, but this means the TC will count pass the first match, generate the interrupt, but has to wait until the 2nd match to reset the TC.  Not sure if I understand this correctly, but in other processors the TC feeds each timer module with its own TC so they are independent...anyone able to shed any light on this?

-Bill

[lpcware]

Content originally posted in LPCWare by williamjsell on Tue Sep 24 14:26:46 MST 2013
that seems the only way to do this, but I guess I was hoping for elegant timer hardware design.  I have created the same effect with the interrupt calling a routine which has a free running counter which does the multiple timing I need.  Sort of the same difference really...thanks for the reply...

[lpcware]

Content originally posted in LPCWare by wells on Tue Sep 24 13:56:00 MST 2013
You don't have to reset the TC on a match. Maybe you can free-run the TC and update your next match event based on the current TC count (accounting for wraparound)?

When MR0 fires (and MR1 is still set to fire later), just clear the MR0 interrupt event and update MR0 with a new event time past MR1. You can toggle the MR0 and MR1 selection to use a single non-resetting terminal counter to generate variable timed events.