LPC55S6x Dual Core Best Practice

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LPC55S6x Dual Core Best Practice

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dingelen
Contributor III

Hi,

I was looking for some more in depth information about how to use the dual cores of the LPC55S6x.

Is there an elaborate document I could read to clear out some of the pitfalls?

Let me point out some grey zones for me.

- it is optimal to let the CPU0 and CPU1 run from different code-sources (flash and SRAMX). But if you don't, what will happen.

   Will one CPU wait for the other to finish the instruction fetch?

   Will there be a collision with some error trap?

   Will false instructions be fed to slave CPU? ....

Now let's say CPU0 is running from Flash and CPU1 from SRAMX.

- Sharing RAM: I would like CPU0 and CPU1 to access a shared area of RAM with data in it needed for both CPUs.

   How do I properly share an SRAM block/range?

   How do I make sure that the only 1 CPU is accessing it at the same time (I've read the part about mutex, but this only seems to work for 1 variable)?

- How about peripherals: CPU0 uses a set of peripherals spread over different buses and CPU1 as well.

   How do I avoid that accessing these peripherals don't cause any bus errors/collisions?

   Are there any mutexes for this?

   Does every bus have it's own hw-mutex or does some software mutex need to be implemented? 

So some help pointing me in the correct direction would be much appreciated.

Thanks

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Sabina_Bruce
NXP Employee
NXP Employee

Hi Tom,

Reviewing your questions here are some comments.

- Generally it is possible to run both cores from flash, but it could have worse performance due to the wait time to access the memory. Since there is only one flash block, and the Core0 & Core1 use the same bus to access it, the slave core image should be assigned to run in a different bus matrix layer from the master core image. Generally, the slave core image is allocated in an independent bank of SRAM and the master core one in Flash.

- If the two CPUs are sharing a single SRAM, you need to make sure that the data memories (including stack and heap memories) used by the two processors are in different address ranges. This document talks about multi-core microcontrollers not specifically about the LPC55s69 but the general idea will be helpful.

- You can also refer to this document for how the LPC55 series communicates between cores.

This document details how to create, build and debug LPC55xx multicore applications using the LPC55S69-EVK LPCXpresso55S69 Development Board.

In addition you can find many examples in the SDK for the LPC55S69 Development board, demonstrating the different ways you can run it using both cores. 

Other documents you may find useful:

AN12358 

AN12326 

Best Regards,

Sabina

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191 Views
Sabina_Bruce
NXP Employee
NXP Employee

Hi Tom,

Reviewing your questions here are some comments.

- Generally it is possible to run both cores from flash, but it could have worse performance due to the wait time to access the memory. Since there is only one flash block, and the Core0 & Core1 use the same bus to access it, the slave core image should be assigned to run in a different bus matrix layer from the master core image. Generally, the slave core image is allocated in an independent bank of SRAM and the master core one in Flash.

- If the two CPUs are sharing a single SRAM, you need to make sure that the data memories (including stack and heap memories) used by the two processors are in different address ranges. This document talks about multi-core microcontrollers not specifically about the LPC55s69 but the general idea will be helpful.

- You can also refer to this document for how the LPC55 series communicates between cores.

This document details how to create, build and debug LPC55xx multicore applications using the LPC55S69-EVK LPCXpresso55S69 Development Board.

In addition you can find many examples in the SDK for the LPC55S69 Development board, demonstrating the different ways you can run it using both cores. 

Other documents you may find useful:

AN12358 

AN12326 

Best Regards,

Sabina

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