Hi, Eugene,
Regarding the ADC clock divider, this is a right configuration:
CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 8U, true);
From the screenshot, you can see the divider is set up as 7.
but it is okay to use the line also:
CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 16U, true);
Because the divider is written with 15, only 3 last bits can be written, so the divider is also 7. I have tested.
Regarding the ADC module after power-down, during power down mode, the ADC is turned off, so after waking-up, you have to reinitialize the ADC so that it can function.
Hope it can help you.
BR
XiangJun Rong
