LPC55S69 : flash memory sector size

[EugeneHiihtaja]

Hello !

I can see flash memory sector size is 32KB and that size is used for define secure access rules and some ROM API is use that size in Erase operation.

But in flashiap1 example from SDK, erasing is done on page ( 512 bytes ) granularity level.

Can I assume that via ISP I can specify uneatable code regions in 32KB granularity.

But If I need to store some own data I can erase/write by 512 byte pages at list.

How independent  those 32KB sectors ?

Can Core0 and Core1 run code from different sectors at the same time ?

Can I erase one sector and continue to run code from other one ?

Or sector/page erasing stall MCU Cores completely and other core can run from SRAM only.

Regards,

Eugene

[Alexis_A]

Hi Eugene,

I will try your questions the best I can:

Can Core0 and Core1 run code from different sectors at the same time ?

Yes, It can but it isn't to stray foward to do this, please check the following post to do this.

Can I erase one sector and continue to run code from other one ? Or sector/page erasing stall MCU Cores completely and other core can run from SRAM only.

You shouldn't have problems with this if you have a good control for it.

Let me know if this helps you.

Best Regards,

Alexis Andalon

[EugeneHiihtaja]

Hi Alexis !

I need time to study that example. Can really Core1 and Core0 share some monolitic bank of flash memory and smootly run own code.

But there is mentioned that "The size of the executable code is limited to the SRAMX size"

Does it means that Core1 executable part and variables fully fit to SRAMX memory if it run from there ?

Regards,

Eugene

[Alexis_A]

The SDK examples are constructed this way, it run from the SRAMX so its limited to the size of this but you can place the code in the flash as it mention in the last part of the thread.

In the following document explain how this is done inside the MCU, check this link.

Best Regards,

Alexis Andalon

[EugeneHiihtaja]

Hi Alexis !

Do I undestand Core0 and Core1 coexistence in right way ?

- if Core0 execute code from Flash memory, Core1 should run from SRAM.

  Code can't be fetched from Flash to both MCU at the same time ?

  Core0 load code of Core1 to SRAM from Flash for execution at any time.

  Core0 can stop Core1, load new code and restart it again without problems.

- LPC55S69 has 4 banks of SRAM and any one can be used for Core1 code execution

 But that bank can't be used by Core0 for any type of accesses, in other case it will be fault.

- Core0 and Core1 communicate via shared SRAM memory on other bank where Core1 is executed

  and some mutex is need for avoid simultaneous accesses.

- It is no clear how Core1 can wakeup Core0 if it in PowerDown mode. What interrupt , event can be used ?

- While Core0 erase/write Flash memory, it is no access to it from any Core. Core0 should run from SRAM some wait loop. ISR need to be in SRAM if they should be served.

Please confirm what is tru and what is not in case of LPC.

Regards,

Eugene

[Alexis_A]

Hello Eugene,

Check my answers bellow:

if Core0 execute code from Flash memory, Core1 should run from SRAM. Code can't be fetched from Flash to both MCU at the same time ?

Correct, to get good performance, the slave core image is allocated in an independent bank of SRAM and the master core one in Flash this avoid the bottleneck for the single access to flash but also if you want to place both codes in flash can be done but with a lower performance

Core0 load code of Core1 to SRAM from Flash for execution at any time.

The master core loads the slave image from flash to SRAM after initialization. 

Core0 can stop Core1, load new code and restart it again without problems.

Yes, as long as the regions are not overlapped

LPC55S69 has 4 banks of SRAM and any one can be used for Core1 code execution but that bank can't be used by Core0 for any type of accesses, in other case it will be fault.

They could, but ideally they shouldn't be accesing the same bank in order to avoid faults and you should make sure both cores are using different address ranges. 

Core0 and Core1 communicate via shared SRAM memory on other bank where Core1 is executed and some mutex is need for avoid simultaneous accesses. 

Yes, the LPC55xx/LPC55Sxx provides a simple hardware means called Inter-CPU Mailbox mechanism for communication, this is pretty similar to a mutex for RTOS. There's an example of this in the SDK.

It is no clear how Core1 can wakeup Core0 if it in PowerDown mode. What interrupt , event can be used ?  

See Chapter 3 - Example from AN12335 and multicore examples from SDK

While Core0 erase/write Flash memory, it is no access to it from any Core. Core0 should run from SRAM some wait loop. ISR need to be in SRAM if they should be served.    

I will suggest to use the Inter-CPU mailbox for this, declare a flag that enable each time one of the cores will modify the flash, this should also be done with the peripherals (UART, SPI, I2C, etc).      

Let me know if this helps you      

Best Regards,

Alexis Andalon