LPC55S69 : disable interrupts while FLASH

[EugeneHiihtaja]

Hi !

All Flash programming code is hidden in ROM and it is not clear some preconditions for have this call in case of interrupts.

/*! See fsl_iap.h for documentation of this function. */
status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
{
if (versionMajor == 2U)
{
runCmdFuncOption.commandAddr = 0x1300419dU; /*!< get the flash program api location adress in rom*/
return runCmdFuncOption.programCommend(config, start, src, lengthInBytes);
}
else
{
assert(VERSION1_FLASH_API_TREE);
return VERSION1_FLASH_API_TREE->flash_program(config, start, src, lengthInBytes);
}
}

Flash memory is not banked and code execution is only possible from SRAM  whiel FLASH_Erase/Program operation.

Is this so ?

But I have system with multiple interrupt sources and ISR routines located in Flash memory .

Should I disable all interrupts by myself or ROM handle this some how in other way ?

Also I have heavy security requirements and should partitioning whole memory in known way.

Where located that small buffer what FLASH_Program is used for wait end of program operation ?

In stack or where ?

Regards,

Eugene

[FelipeGarcia]

Hi Eugene,

When handling (writing or erasing) Flash, you should not execute code at the same time. This also applies when the code is executed due to interrupts. Therefore, if the interrupts are not executed from RAM or they are located in the same flash block you are writing or erasing, it is recommended to disable interrupts to prevent a failure due to the interrupt trying to use the unavailable Flash.

Best regards,

Felipe

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[EugeneHiihtaja]

Hi felipegsoto‌ !

By using common sense, yes interrupts should be disabled like we did on K82 when use it.

But LPC is not offers source code for flash routines and there are part of romcode. It cause huge amount of questions and rumor

how tere are really done.

1. I enable 2kHz Systick interrupts and 1kHz from OS timer and FLASH_write/erase routines is not failed.

   It can be so that interrupts disabled some how inside FLASH API. ( K82 fail almost immideatelly )

2. If I try to utilize the same  32KB block for erase/write of my data what partially used by code and while write always have 

Ecc error.

It seems to me internal flash splitted on some independant 32KB blocks even whole flash are not banked.

3. In any case flash memory should have wait loop in sram for loop end of flash operations.

   Where it is located ? In stack or some area is occupied what is not disclosed in UM.

4. We have very have usage of TZ secure gates and should know what access right should be given to memory/peripherals.

    And executable rights for ram where is loop as well.

5. Disabling of interrupts require privileged execution and it cause problems as well, becouse our TZ code need to be run with User privileges.

it means we need to know case if we use 32KB aligned flash block, should we disable interrupts or not

and where wait loop is allocated. And does FLASH API is used any other SRAM memory or only stack ?

For Secure SPI of ROM some SRAM area is specified  but for FLASH is not documented in UM.

So you can see that implementing any adequate application on LPC require little bit more details than mentioned in UM

and DS and it is quite difficalt to find out everythyng via testing.

Regards,

Eugene

[FelipeGarcia]

Hello Eugene,

Please check the below extract from UM.

When the user application code starts executing, the interrupt vectors from the SRAM are

active. Before making any IAP call, disable the interrupts. The IAP code does not use or

disable interrupts.

Regarding the SRAM area used by the Flash API, I see you have asked the exact same question to my colleague in this thread. Please do not ask same question in different threads and to different people to avoid double work. Indeed, this information is not stated in documentation, we will ask this internally and provide response whenever we received any feedback.

Regards,

Felipe

[EugeneHiihtaja]

Hi felipegsoto‌ !

Thank you !

I hope usage of Flash API is not reguire reservation of SRAM as mentioned  in chapter 8.3.4.2 RAM used by the ISP command handler.

We have lack of memory already and this question important to us.

I can see LPC55S69 is new chip for NXP community as well. It is quite difficult to get right answer and some questions are remains unanswered at all. I should refresh those for be sure if it taken to processing in non-formal way. 

UM ans DS updated all the time and consultants gain experience and every new day bring  other vision for the same question

and I would like to be updated.

Regards,

Eugene

[FelipeGarcia]

Please refer to this thread for answer regarding RAM usage of Flash API: LPC55S69: RAM reservation for ROM API operations