LPC55S69 : UM2.0 & Power-down mode & GPIO lines

[EugeneHiihtaja]

Hi !

We have got UMv2.0 for LPC55S69 and it seems to me it is not updated in case if subj.

During our testing was find out that GPIO lines loze direction and all outputs starts to be inputs if MCU go to PowerDown mode.

Does this mentioned in UM2.0 somewhere ?

We should be sure id this a not errata , this is feature.

Or this will work in different way in new silicon revision ?

Regards,

Eugene

[xiangjun_rong]

Hi, Eugene,

I have asked the AE team, this is the intrinsic  feature of the LPC55xx family rather than a bug.

You observed that the GPIO output pin loses  it's logic and becomes input mode during power-down mode and deep power-down mode, the phenomenon can be explained by the power supply internally.  The GPIO module is powered by PD_CORE power domain, after power-down instruction is executed, the PD_CORE power domain is lost, in other words, the GPIO module is power off. After waking-up, the PD_CORE power domain is recovered, so you have to reinitialize the GPIO module. Pls refer to page Power Domain : 1. CORE (PD_CORE).

The SYSCON and IOCON modules are powered by the PD_SYSTEM power domain, after power-down instruction is executed, the PD_SYSTEM and PD_AO power domains are valid, in other words,you do not need to initialize the SYSCON and IOCON modules after waking-up from power-down instruction.

I attach the Power Domain doc, hope it can help you

BR

XiangJun Rong

[EugeneHiihtaja]

Hi xiangjun.rong‌ !

Thank you ! Logic is clear but due importance of GPIO line, it have sense to write this explicitly in UM.

What you mean "I attach the Power Domain doc" ? I can't see any attachment.

Regards,

Eugene

[xiangjun_rong]

Hi, Eugene,

This is what I can see for the ticket. The doc is 02_LPC5500_LOW_POWER_MODE_V1.4.pdf

BR

XiangJun Rong

[EugeneHiihtaja]

Hi xiangjun.rong‌ !

Yes , as usually it its visible like you post.

But file is not visible yet. may be replication take some time.

Regards,Eugene