Hi,
I'm doing a study on contention on the LPC55S69 architecture. Could someone clarify me if the the SRAMs in this board are dual-ported?
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Hello @raz3l
The SRAM in lpc55ss69 is not dual-ported, while if you want to share SRAM between two cores, you can refer to SDK demo "lpcxpresso55s69_erpc_matrix_multiply_rpmsg"
BR
Alice
hi,raz3l
Can you further describe your question about what the LPC55S69 does and what dual port means and is used for? To help you in more detail.
BR
Xu Zhang
Hi @Xu_Zhang ,
By "dual-ported SRAMs," I mean if the SRAM memory elements for data (SRAM0-SRAM3) allow for two independent read or write operations to occur simultaneously. In the context of the LPC55S69, my concern is whether both cores of the microcontroller can access the SRAM concurrently, without causing contention or access conflicts.
In simpler terms, I'm trying to determine if the LPC55S69's SRAM architecture supports simultaneous read and write operations from both cores (e.g., the main core and the co-processor core) without one core blocking the other.
Thank you!
hi,raz3l
To achieve the best working performance, allocate the memory blocks of code and data for both cores in a suitable way and reduce the arbitration of the accessing bus in the hardware system.
In the hardware system diagram, the memories are divided into blocks and connected to the AHB bus matrix separately. Using this design, different bus masters can access different memory blocks simultaneously, without any arbitration delay.
BR
Xu Zhang
Hello @raz3l
The SRAM in lpc55ss69 is not dual-ported, while if you want to share SRAM between two cores, you can refer to SDK demo "lpcxpresso55s69_erpc_matrix_multiply_rpmsg"
BR
Alice
Thank you Alice!