Hi @Xu_Zhang ,
By "dual-ported SRAMs," I mean if the SRAM memory elements for data (SRAM0-SRAM3) allow for two independent read or write operations to occur simultaneously. In the context of the LPC55S69, my concern is whether both cores of the microcontroller can access the SRAM concurrently, without causing contention or access conflicts.
In simpler terms, I'm trying to determine if the LPC55S69's SRAM architecture supports simultaneous read and write operations from both cores (e.g., the main core and the co-processor core) without one core blocking the other.
Thank you!