LPC55S69 : Flash programming constrains

[EugeneHiihtaja]

Hello !

1.

UM chapter 4.6.5.2 give Note :

"

Note: Flash ERASE and PROGRAM operations must be performed with a system clock
below or equal to 100 MHz.

"

So if I have clock 150 Mhz , I shouldn't erase and program flash memory. Is this so ?

Is exists any examples how-to change MCU clock on fly safetly ?

I assume peripherals clocked from independent clock source  and we should adjust system clock and something else in safe way. How to do this on fly ?

2. Flash API is integrated to Bootcode and it is not clear if after erase/write operations some caches/flash accelerators

   should be cleaned/invalidates. Like it was done for K82.

  Or everything is done inside those APIs and I should disable/enable interrupts for avoid ISR execution from Flash memory if I need to ?

3. If I undestand right and minimal erasable unit of Flash memory is  512 bytes.

  Does exists any other bigger erasable sector ?

Or if I would like to erase 8KB space , erase time will be 16*21ms ?

Regards,

Eugene

[Sabina_Bruce]

Hello Eugene,

Here are the answers to your questions:

1.So if I have clock 150 Mhz , I shouldn't erase and program flash memory. Is this so ?

Is exists any examples how-to change MCU clock on fly safetly ?

I assume peripherals clocked from independent clock source  and we should adjust system clock and something else in safe way. How to do this on fly ?

Yes, it is a flash erase/programming constraint to be 100MHz or less for flash/erase operations.

In clock_config.c you can find void BOARD_BootClockPLL150M(void) function which configures system clock to 150 MHz, and void BOARD_BootClockPLL100M(void) which configures system clock to 100 MHZ. Those are example codes already implemented in the clock config. I would recommend to use the power_manager_lpc example provided in the SDK which describes how to change between different clocks. 

2. Flash API is integrated to Bootcode and it is not clear if after erase/write operations some caches/flash accelerators should be cleaned/invalidates. Like it was done for K82. Or everything is done inside those APIs and I should disable/enable interrupts for avoid ISR execution from Flash memory if I need to ?

The flash accelerator buffers are automatically invalidated at the beginning of any flash programming or erase operation.  In the SDK you can find an driver example of the FLASH: flashiap1. Here it is shown that it is not necessary to clean caches. Application code, especially interrupts, can continue to run from other memories during flash erase/write operations. 

3. If I undestand right and minimal erasable unit of Flash memory is  512 bytes. Does exists any other bigger erasable sector ? Or if I would like to erase 8KB space , erase time will be 16*21ms ?

The FLASH_Erase function receives a 32bits parameter: lengthInBytes, that is the limit. The only requirements is that must be word-aligned. You can see an example in the User Manual in page 231, where the lengthInBytes parameter is 0x400

Could you please clarify how you are calculating the erase time. The datasheet provides the typical erase time for 1 page(512bytes) which 2ms.

Best Regards,

Sabina

[EugeneHiihtaja]

Hi Sabina !

Yes I can see new DS has updated timing values for flash memory and now can I say like this:

For erase 256KB space I need to wait 2*512 =  1024 ms ( ~1s) and write data after that - 512 bytes/ 1.09ms.

So it is not possible to erase and write faster ? And similar timing we might have inside bootloader when perform ISP update ?

It is not clear if booloader is able to receive data when flashing/erasing ongoing e.g. SPI interrupts located in SRAM.

Is this so ? Or what is theoretical speed for SPI data transfer  and ISP flashing  ?

Could you explain tricks what need to update system clock on fly. If we see powermanager example in case of Power-Down:

DEMO_PreLowPower();
POWER_EnterPowerDown(APP_EXCLUDE_FROM_POWERDOWN, 0x7FFF, WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1,1);
DEMO_PowerDownWakeup();
APP_InitWakeupPin();

Looks like after wakeup you switch to FRO12Mhz oscillator and do not return back to 150Mhz.

And it is not so clear if Power-Down mode need if you would like to switch  from 150 to 100 and back.

Or it should be done via FRO12Mhz.

What kind of effect have those pre/wakeup functions for GINT0/1 pin detection ?

What should be really disabled while transistition  of system clock from 100 ->150 -> 100 Mhz ?

I assume peripherals has independent clocks and only MCU need some sequences while systemclock changes.

Regards,

Eugene

[Sabina_Bruce]

Hi Eugene,

So it is not possible to erase and write faster ? And similar timing we might have inside bootloader when perform ISP update ?

These values described in the datasheet are typical values. It is possible that it may be slower or faster but not by a big difference. This depends on how optimized the application is. 

It is not clear if bootloader is able to receive data when flashing/erasing ongoing e.g. SPI interrupts located in SRAM. Is this so ? Or what is theoretical speed for SPI data transfer and ISP flashing  ?

I do not understand this question. Could you please clarify what do you mean by recieve data when flashing/erasing. Do you mean during a flash operation such as programming or erasing, you are receiving data? 

What should be really disabled while transistition  of system clock from 100 ->150 -> 100 Mhz ?

I assume peripherals has independent clocks and only MCU need some sequences while systemclock changes.

You need to have both clocks running in order to switch from one to the other.  The following should be considered for the generation of the clocks.

Also, to make it easier you may use the clock tool provided in MCUXpresso IDE. To make the code necessary to use the clock at certain frequencies.

Best Regards,

Sabina

[EugeneHiihtaja]

Hi Sabina !

I mean ho-to optimized bootloader internals ?

You can receive data block and start to write it. Meanwhile the next data chunk can be received to RAM and write starts immediately after previous block is written.

Or it can be done in simple way, receive data, write it, receive next block and etc.

I can see bootloader SPI flashing expect SPI clock 2Mhz and require nIRQ pin for indicate busy step.

But what is maximum flashing speed ? How fast I can flash MCU via SPI ?

 512KB -> 1024 of 512 bytes block -> * ( 2ms erase + 1 ms write + data transfer) -> ~3s

What speed I can get on practice by using ISP mode ?

Regards,

Eugene

[Sabina_Bruce]

Hello Eugene,

You can receive data block and start to write it. Meanwhile the next data chunk can be received to RAM and write starts immediately after previous block is written.

As long as you are not attempting to read and write the same block you can implement it this way.

But what is maximum flashing speed ? How fast I can flash MCU via SPI ?

 512KB -> 1024 of 512 bytes block -> * ( 2ms erase + 1 ms write + data transfer) -> ~3s

What speed I can get on practice by using ISP mode

These are the typical speeds shown in the datasheet. However, these values are not considering the time before the actual erasing and programming occurs. So this value that you have calculated is an approximation it will be either more or less depending on how you implement your application. There is not a max flash speed given as these values can vary and we do not provide a minimum or maximum speed. Please take into consideration what is provided in the datasheet as well as the time it takes to boot in isp mode, execute the proper commands to setup for flash commands.

Best Regards,

Sabina