Hi @qingyunliu
1. I did not understand if you are refering: how the capture is triggerd to get the value or how the input signal is provided to the mcu.
2. The CAP frequency limit is defined with the APB bus clock. On chapter 25.6.11 Count Control Register of the user manual says "the frequency of the CAP input cannot exceed one half of the
APB bus clock" also on chapter 4.4.1 Clock generation says "The maximum allowed frequency for main clock and system clock (to CPU0, CPU1, AHB bus, Sync, etc.) is 150 MHz".
I'll be waiting for the clarification to question 1.
Best Regards, Miguel.