LPC55S66 : how-to get reset reason and etc.

[EugeneHiihtaja]

Hello !

Just few question about LPC55S66 what are not clear from specifications.

1. Does it possible to identify reset reason of MCU ? 

  In K82 it was possible to identify what was reason of boot :

  cold reset, sw reset, watchdog reset or external pin reset.

2. All FLEXCOMM interfaces mentioned to be supports USART and any USART can be configured like UART

   without any problem ? I can see one bit in configuration but ...

3. In one page mentioned that programm flash has page size 256 bytes - other 512 bytes.

   I think internal flash has minimal erasable unit as 512 bytes and with activated PRINCE module

   I can erase/write flash memory on fly without any problem.

 Erase/write time is quite long and what is MCU execution behaviour in this case ? It is stall ?

And I should wait end of operation in SRAM memory loop ?

How it can effect Core1 if Core0 update some flash pages ?

Should Core 1 is also execute code from SRAM if Core 0 erase/write program memory ?

What is also not so clear if Core0 and Core1 execute code from the same SRAM/Flash memory  ?

Or SRAM banks should be different and flash memory resized some how ?

4. Basically any GPIO pin can be used for wakeup Core 0 from Power-down mode if

   this pin is added to GINT0 or 1 group.

5. What exact means WAKEUP_FLEXCOMM3 support ?

   For example SPI wakeup due clock eghe on SCK line and etc.

  But wakeup of MCU from Power-down mode take > 300 us and some SPI data might be lost already.

 Or how so long wakeup time is handled by FLEXCOMM controller ?

6. Is any limitation for some peripherals/memory how the can be resized between Core0 and Core1 ?

   Or just access right like secure/NS/Priv/nonPri is define accesses ?

Thank you !

Regards,

Eugene

[Alice_Yang]

Hello 

2. any USART can be configured like UART  without any problem ?

-> Yes.

3.  I think internal flash has minimal erasable unit as 512 bytes and with activated PRINCE module

   I can erase/write flash memory on fly without any problem.

-> YES.

The Slave code(core 1 ) will run from RAM and must not conflict with memory used by the
Master project ( Core 0) . You can have a look at the Multiple core demo under SDK.

4. Basically any GPIO pin can be used for wakeup Core 0 from Power-down mode if

   this pin is added to GINT0 or 1 group.

-> Port 0 and Port 1.

5. What exact means WAKEUP_FLEXCOMM3 support ?

   For example SPI wakeup due clock eghe on SCK line and etc.

-> SPI interrupt is wake-up from low power mode.

From the datasheet of this chip:

" The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up
from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)
wake-up handler. "

So about  SPI interrupt wake-up, the time is from interrupt to the chip wake as active mode.

6.

-> The LPC55S6x device includes a second instance of Cortex M33. The configuration of
this instance does not include MPU, FPU, DSP, ETM, Trustzone (SECEXT), Secure
Attribution Unit (SAU) or co-processor interface. It supports the same debug levels and
interrupt lines as the primary CPU.

1. Does it possible to identify reset reason of MCU ? 

-> I also haven't find the related register, I will ask SE team, then reply you .ASAP.

Have a great day,
TIC

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[EugeneHiihtaja]

Hello !

I think reset reason register is exists and visible on page 267 of UM.

Alice,

"

The Slave code(core 1 ) will run from RAM and must not conflict with memory used by the
Master project ( Core 0) . You can have a look at the Multiple core demo under SDK.

"

Does it mean fact that Core1 is not able to run from Flash memory in any case if Core0 is use it ?

And in almost all examples, Core 1 code is executed from RAM ?

So Flash memory is monolitic and not banked . It also mean that write/erase operation is stall execution of Core0 ?

But all flash API are located in ROM and it is not visible how all interrupts are enabled and disabled.

Could you clarify Flash memory behaviour in case of sharing it between Core0&1 and write/erase operations.

Thank you !

Regards,

Eugene

[Alice_Yang]

 Hello Eugene Hiihtaja,

"Does it mean fact that Core1 is not able to run from Flash memory in any case if Core0 is use it ?

And in almost all examples, Core 1 code is executed from RAM ?"

->Yes. For LPC55S66 there is only one flash bank, so we can not running two or more cores main code on one storage bank, because if both core need catch data or command, flash can not response both core request, the core will be stopped and generate fault. Core1's app code storaged in Flash, once power-up, core0 will be startup first, then copied the core1 image into SRAM area and run core1.

Have a great day,
TIC

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[EugeneHiihtaja]

Hello Alice !

Basically it is closed loop and Core1 can use SRAM only.

Bootloader starts on Core0 only and after that able to jump to Core0 and in secure mode starts someting on non secure side.

It means only SRAM remains for Core1.

Can Core1 starts when Bootloader in ISP mode ? Any hooks or tricks ?

 While ISP update I need Core1 running and track some pins.

After ISP update, Core0 apply TZ configuration and find out that Core1 is active already.

is this possible ?

Regards,

Eugene

[Alice_Yang]

Hello Eugene Hiihtaja,

The bootloader code in BOOT ROM is Factory programmed, we only can use , can't 

change it. In ISP mode, there is no code enable Core1, so can start Core1 in ISP mode.

Have a great day,
TIC

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