LPC55S28 Lower Power RTC Battery Backup when using ROM bootloader

[guitardenver]

I am using the LPC55S28 MCU. I need a battery backup for the RTC. Since there is not a dedicated RTC power pin, our MCU must go into a deep power down mode each time power is removed from the device. If I do not, the current VBAT pins draw is way to much for a coin cell battery. I need something that will last 4-6 years on a 1632 coin cell. My battery backup only supplies the VBAT power pins (only 3 pins).

I have the VBAT BOD configured and when the interrupt hits, I shut everything down and go into a deep power down mode. Which makes the VBAT only draw about 720nA. Which is great and works really well. 

I also want to use the ROM secure bootloader. I want to use the USB port for firmware updates. Instead of making a custom bootloader I would love to use the one built in and use the NXP secure provisioning tool and encrypted firmware files. 

My questions:

1. If the MCU boots into the ROM bootloader, via the ISP pin, what happens when power is removed while in bootloader mode?

2. How can I guarantee that the battery will not end up drawing a ton of current if my application code is not running with it's BOD interrupt?

3. Any other suggestions to use the ROM bootloader and still have a robust battery backup only for the RTC?

[guitardenver]

In my design, I only power VBAT with the battery once powered down. Via diodes to to protect it from feeding VMAIN as well. The issue is that if you boot into ROM bootloader, and power is removed, VBAT is drawing almost 10mA. It's only when I am able to put the MCU into deep power down mode on the brown out detection that the current draw is 1uA or less. 

[Harry_Zhang · Accepted solution]

Hi @guitardenver 

Thank you for sharing the schematic.
VBAT_PMU and VBAT_DCDC/CORE are tied together and fed from the coin cell through a diode.
In ROM bootloader mode, the MCU is in full active state (PD_CORE + PD_SYSTEM powered).When VDD_MAIN collapses suddenly, the PMU doesn’t automatically force Deep Power Down.
The internal regulators try to keep PD_CORE alive using VBAT as a fallback.
So If the MCU is in ROM ISP mode and power is removed, there’s no software hook to enter DPD. The PMU doesn’t auto-gate PD_CORE because it assumes VDD will return quickly.
If you only need RTC backup, do not feed VBAT_DCDC/CORE from the coin cell.
Tie VBAT_PMU to the coin cell, but leave VBAT_DCDC/CORE connected only to VDD_MAIN.
This ensures PD_CORE cannot draw from VBAT.

BR

Harry

[guitardenver]

Thank you for the information!

I will connect VBAT_DCDC and VBAT_DCDC_CORE to the main external power only. And only connect the VBAT_PMU to the battery. 

[Harry_Zhang]

Hi @guitardenver                                                                                                                                         

On LPC55S28, the chip is split into power domains. When VDD_MAIN goes away, only the Always‑On (PD_AON) domain—powered from VBAT_PMU—remains. PD_AON contains the PMU/PMC, RTC, OS event timer.

So Power removed in ROM ISP: ROM stops; non‑AO domains lose power; AO domain keeps RTC on VBAT; next wake is a cold boot with ROM re‑deciding boot source. No ROM-induced VBAT drain provided you block back‑power from external interfaces.

You can refer to the Power Management on LPC55S3x/LPC553x.

If you want to guarantee that the battery will not end up drawing a ton of current if my application code is not running with it's BOD interrupt.

I think VBAT must feed only the AO domain. Make sure the coin cell feeds VBAT_PMU via a diode/ideal‑diode and does not accidentally source VDD_MAIN or any external rails through pull-ups or transceivers.

You can refer to the Hardware Design Guidelines for LPC55(S)xx.

BR

Harry