LPC55S06 Ramp Time Clarification

[Zilog2]

Hello,

I'm going to design a new board based on LPC55S06JHI48QL.

The Datasheet (and the Errata too, "VBAT_DCDC.1 Functional Problem") states for power-up ramp condition a mimimun of 2,6 ms to cover all possible condition (from -40Celsius up to 105). The buck converter regulator that I use has a typical soft-start time of 200us and I cannot switch to a different part number. 

I am going to add some redundant circuitry to accomplish the requirement, increasing overall cost and complexity.

Maybe I misunderstood the requirement? Or is there some quick fix from NXP?

Thanks in advance

[Zilog2]

Hello Daniel, thank you for you reply. I needed a confirmation of the correct understanding. My problem arises because low cost DCDC converters we normally use (and more important, we are able to find in distribution in components' shortage times) have  fixed ramp-up tyme, typical 200us-1ms. So, as you wrote, it is a matter of fact that I can accomplish the 2,5ms ramp time requirement only adding additional components. Voltage regulators with programmable soft start are quite overkilling in our application, considering the overall money budget for the application, the very good low power consumption of the LPC55 and mainly the fact that we start from quite high voltages (batteries with 30 Volts with overvoltages due to motors on the power lines).

Last question... To recover the 100% of potential cases can you confirm me that a simple reset is not sufficient and I need a power cycle? 

Meanwhile, I'll add some component and perform ramp time validation...

Thanks a lot!

.

[Daniel-Aguirre]

Hi,

Can you elaborate more on "recover the 100% of potential cases"? Is this related to wake up the system from a lower power mode?

If so, the system does not need a power cycle to wake up from the lower power modes, just be sure to configure a wake-up source for it to not require a power-cycle.

But please, let us know if this was not the question you were asking.

[Zilog2]

Hello,

no I was just thinking to the case when the marginality occurs, that is ramp time requirement is violated (the ramp is too step for some unpredictable reason, maybe an extremely low temperature or other cause) and the LPC is hanging in this grey zone... How recover from this? I suppose a simple reset is not sufficient... --in this case I expect that a power cycle activated externally may solve the issue (i am using LPC55 to realize a smart sensor).

[Daniel-Aguirre]

Thanks for the clarification.

That is correct. If the ramp-up is not fulfilled, the need of a power-cycle to compensate the problem is the way to do it.

We do apologize for this situation.

Let us know if there is something else we can help you with.

[Zilog2 · Accepted solution]

OK it is clear now. Thank you very much for your support.

BR

[Daniel-Aguirre]

Hi,

As you are saying, this is needed for the system to have a proper behavior. If not followed, there could be undefined states caused by the faster ramp up on power-up.

As said in the Errata, there is no work around for this condition, this needs to be followed in order to ensure the correct behavior of the system.

Just curious, this soft-start you are talking about is normally controlled by an internal register or by an external capacitor/resistor, is there no other way of increasing this soft start on your buck converter?