The LPC5528 is Harvard Architecture, but it has some RAM on the Program memory bus, as if it were Von Neumann, and I can't find any explanation of why it is there. Can it be used just like the RAM on the Data side?
Hello
This post might solve your questions: https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/8615/how-to-explain-the-...
For more detailed information I suggest you to check the Cortex-M33 Technical Reference Manual and the Armv8-M Architecture Reference Manual.
https://developer.arm.com/ip-products/processors/cortex-m/cortex-m33
If you have more questions do not hesitate to ask me.
Best regards,
Omar
Still none-the-wiser.
If RAM is for data, what is it doing on the program memory side of the bus?
You can execute code from it. As RAM is typically zero wait state, it flash is not, it can run at full core speed, so can be used for time critical functions.
this may not be the only reason, but it is what we have done.
I was just thinking of using it for data.
I was looking for a device with plenty of on-board RAM, so I could avoid having to use an external serial static RAM, and I needed all 256k for data.
Could the stack go there?
It should work, but I'm not sure about the access timings. Often, there is a penalty for accessing data from the 'program' bus or for accessing code from the data bus. It might be worth writing a small program to see if there is such a penalty.