LPC551x Power down GPIO behavior

[marmon]

I need to understand the behavior of the GPIO while the LPC5516 is in power down mode.  However, there seems to be a contradiction between the datasheet and user manual for the state of the GPIO pins:

From the datasheet (Rev. 1.8 — 29 September 2022), 7.21.3 Power-down mode :

The GPIO logic level remains static since power domain system
(PD_SYSTEM) remains powered.

From the user manual (Rev. 1.7 — 26 August 2022), 13.3.5 Power-down mode:

The GPIO logic level does not remain static in power-down
mode. All GPIO pin state will be logic '0' in power-down mode.
All IOCON registers and peripheral registers

I need to maintain some GPIO in a defined state while being in power down but from experimentation, they seem to behave as the user manual is stating, that is they don't retain the state they had prior to entering the power down state.  However, as far as internal weak pull-up/pull-down are concerned, they seem to hold on their previous state if they are enabled in the GPIO pad. 

So am I correct to assume that I can rely only on enabling the pull-up or pull-down to maintain the output state of GPIO during power down, in what seems to be a contradiction with the datasheet?

[RaRo · Accepted solution]

Hello @marmon,

Thank you for letting us know about this. We will let the team in charge to know about this contradiction in the documentation.

So am I correct to assume that I can rely only on enabling the pull-up or pull-down to maintain the output state of GPIO during power down, in what seems to be a contradiction with the datasheet?

As you mentioned, in power-down mode the GPIO module "does not remain static" as stated in the LPC55S1x/LPC551x User manual. You could remain the GPIO value to pull-down or pull-up through GPIO configuration register, when enter power-down mode.

Thanks again for the feedback.

Best regards, Raul.