LPC54xxx Output SCL is lost.

[t-umetsu]

Hi Them.

I am using LPC54605 MCU.
I encounted a problem that MCU output SCL is lost.(See below)
I want to know what is happons. 

i2c_signal

Additional informations.

• MCU LPC54605J256
• MCUXpresso IDE v11.2.0
• SDK version 2.8.2
• I2C Master transfering via using I2C_MasterTransferNonBlocking() function.
• Baudrate is 100kbps
• MCU clock is internal oscillator. (FRO oscillator 96MHz)
• FlexComm source clock is fro_12m (12MHz)
• Other using peripherals (USB, GPIO, ADC, CTIMER)
• This problem often occurr with driving other device (It is heater controled by GPIO).
  I think that this cause is depend on our system. But, why MCU lost output SCL?
  Its signal is generated by FlexComm Peripheral.
  
  
  

static volatile status_t I2C1TransferStatus = -1;

void init_i2c(void) {
    CLOCK_AttachClk(kFRO12M_to_FLEXCOMM8); // Set clock source to fro_12MHz
    RESET_PeripheralReset(kFC8_RST_SHIFT_RSTn); // Reset FlexComm

    i2c_master_config_t masterConfig;
    I2C_MasterGetDefaultConfig(&masterConfig);
    masterConfig.baudRate_Bps = 100000; // 100kHz
    masterConfig.enableTimeout = true;
    I2C_MasterInit(I2C8, &masterConfig, 12000000);
    I2C_MasterTransferCreateHandle(I2C8, &I2C1MasterTransferHandle,
            i2c_request_done, NULL);
    return ;
}
static void i2c_request_done(I2C_Type *base, i2c_master_handle_t *handle,
        status_t status, void *userData) {
    /* Signal transfer success when received success status. */
    I2C1TransferStatus = status;
}
bool transfer(i2c_master_transfer_t *masterXfer) {
    status_t stat = kStatus_Fail;
    I2C1TransferStatus = -1;
    stat = I2C_MasterTransferNonBlocking(I2C8, &I2C1MasterTransferHandle, masterXfer);
    if (stat != kStatus_Success) {
        return false;
    }
    while (I2C1TransferStatus == -1) { // Is transferring?
        // do nothing.
    }
    return I2C1TransferStatus == kStatus_Success;
}

[t-umetsu]

Thank you for reply.

We tried with slow baudrate. For example, 10kbps.
We seen same phenomenon. So we think that the cause is not baudrate.

We approach other method and resolved this problem. 
This bus hung up was occurr with driving high current near i2c bus. So we reduced effect of its line. Then, its not occurred.

What I'm wondering is SCL is generated by MCU peripheral on master transfer, but one pulse lost.
It's hard to explain in words, so take a look below.

We imagine one of the following.(This is just our imagination.)

1. Driving clock of FlexComm was disordered by external noise.
2. SCL change to L by external noise, clock is lost. Same time, clock stretch is occurred. One pulse of SCL was lost.
3. If FlexComm is inteligently watch SCL line.
   FlexComm peripheral judged SCL high state is end because detected L of SCL just after release SCL.
   Peripheral change to next state (SCL to L). Therefore SCL is lost.

[frank_m]

> This bus hung up was occurr with driving high current near i2c bus. So we reduced effect of its line. Then, its not occurred.

If that is true, than the issue is not related to clock stretching.
Rather the synchronisation and the ACK signal got lost.
Many I2C slave devices are simple state machines, and never re-synchronize without power cycle or other specific measures.

[Omar_Anguiano]

There are situations where an I2C slave is not able to co-operate with the clock speed given by the master and needs to slow down a little. This is done by a mechanism referred to as clock stretching. 
This clock stretching might be the reason why SCL is held. 

To test this, you might slow down the I2C bus baudrate to confirm this. 

Best regards,
Omar

[t-umetsu]

Thanks for explanation.
I was misunderstand about clock stretch. I understood that the cause of this behavior is due to the slave device.
I don't understand that it is possible for a slave device to shorten the cycle of one sequence (9bits=Addr+RW+ACK)..Because I don't think the duration of the sequence will change even if the slave device keeps SCL low.

[frank_m]

> I don't understand that it is possible for a slave device to shorten the cycle of one sequence (9bits=Addr+RW+ACK)..Because I don't think the duration of the sequence will change even if the slave device keeps SCL low.

Your understanding is correct so far.
The number of transferred bits does not change, as this is crucial for the functionality of the bus.
If only 8 cycles are visible, it is likely that the master catched and interpreted a noise spike as clock pulse.

For clock stretching, the slave keeps SCL low when he detects clocking issues. This protracts the transfer, but does not change the sequence of logic levels.

If you have EMV issues due to switching of high currents nearby, perhaps you can reduce the I2C clock frequency further, and/or add some RC lowpass filters to increase robustness.