LPC546XX: ROM bootloader and memory map

[giusloq]

Bootloader in ROM is placed at 0x0300 0000 address. What exactly happens immediately after a reset?

Cortex-M should load vector table (with SP address and startup code) from VTOR register that should zero after a reset. In this case I don't explain how the bootloader in ROM can start if it is placed at 0x0300 0000.

One possibility is that VTOR reset value is 0x0300 0000, but I don't think.

Another possibility is that Boot ROM memory is mapped to 0x0000 0000 after a reset and during the boot process, this mapping is disabled.

Please, explain what happens exactly.

Does ROM Bootloader use some SRAM if all ISP pins are at the default value?

[jay_heng]

ROM needs some SRAM region for its DATA/BSS/STACK, but it doesn't effect user application, as the SRAM region will be released when exiting ROM except below cases:

the ISP and IAP software use parts of the on-chip RAM.

- Memory for the ISP commands is allocated dynamically at the end of SRAM0.

- Flash programming commands use the user stack space and may use up to 128 bytes growing downward.

So if you set ISP pin to default 3'b000, it is flash boot mode (no ISP), and if your app doesn't contain IAP function, then there is nothing to do with ROM SRAM usage.

[giusloq]

ROM needs some SRAM region for its DATA/BSS/STACK, but it doesn't effect user application, as the SRAM region will be released when exiting ROM except below cases:

What do you mean with "released when exiting ROM"? If Boot ROM writes something in SRAM, I need to know which part are used.

I'm trying to use .noinit section to preserve the content of some variables after calling NVIC_SystemReset(). However it seems that some parts of SRAM don't retain their content after a system reset and the only cause I can think of is the Boot ROM.

[DanielRuvalcaba]

Hello

Can you please give me more information about what parts of the SRAM you are having problems with?

Best regards, Daniel.

[giusloq]

Can you please give me more information about what parts of the SRAM you are having problems with?

It seems to me that the first 4kB space of SRAM is untouched after a reset, while the next 4kB SRAM space is reset to zero after reset.

At first, linker put the noinit variable in the second 4kB space and I found the issue: even if it was declared noinit, its value was always bring to zero after a reset.

After moving the variable in the first 4kB SRAM space, the problem goes away and the value in the variable was maintained after a reset.

So I suspect the ROM bootloader really uses some part of SRAM. So my original question.

[jay_heng]

The boot loader code is executed every time the part is powered ON or reset, it is SoC system level implementation for ROM boot, you don't need to worry about the initial VTOR value after reset.