if I set transfer delay 3,4,5,9,10 the clock pulse are 16 pulses why?
and I set transfer delay 1,2,6,7,8 the first pulse width should be High.
Hi,
If you want to validate the FRAME_DELAY time, you have to set the EOF bit in FIFOWR register for each transfer.
Hope it can help you
BR
XiangJun Rong
