LPC54018 EMC track length matching

[adrian_lavin]

We're using LPC54018 with external parallel NOR flash and SDRAM. The address bus is different lengths for both does the track lengths need to be matched to a particular accuracy. Also the JTAG and BOOT share pins with the bus is there any guidelines for managing connection of these to the data bus?

[diego_charles]

Hi Adrian

I apologize for the delay,

At this moment you may have found the AN12026 SDRAM interface to LPC546xx external memory controller

However , I am able to point out the  chapter  5  Schematics, PCB design tips and suggestions, that provides guidelines for trace lenghts , trace impedance and compensation for clock fligth time.

If I can help further, please do not hesitate to reply.

Regards,

Diego

[adrian_lavin]

Hi Diego,

Thanks for the replay, yes I have reviewed chapter 5 and would the following be correct:

For our design we have one SDRAM, one NOR Flash (shares A0-A14, D0 to D15 and WEN with SDRAM), JTAG (shares D0 to D4 with SDRAM) and Boot pins (share D2 to D4 with SDRAM).

Layout will be MCU at one end the SDRAM at the other end and the Flash, Jtag, Boot in between the two devices.

The introduction to chapter 5 mentions branch stubs of no more than 2inches, does this refer to the track shown in orange below, is this the limit for the length on each stub or total?

CLK0 routed from the MCU to the SDRAM directly with trace impedance of 60-80ohms. Length is not critical as it can be tuned with internal delays.

All other signals routed with impedance of 80-100ohms

In section 5.3, if the data bus is longer than 1.5inches total (does this include the stub lengths?) use series termination resistors, is there a recommended value? Is this only for the data bus signals to any other signal have to comply with this requirement?

Section 5.4.1, Rule 1, does the 2 inches of length matching refer to the trace length directly from the MCU to the SDRAM (just the red trace below) or does it also include the stub lengths as well? For example can EMC_D0 from MCU to SDRAM be two inches longer or shorter than EMC_CAS?

Thanks and Regards,

Adrian

SULZER CONFIDENTIAL

[diego_charles]

Hi Adrian,

Thank you for your reply, please provide me additional time to provide you my feedback.

Regards,

Diego.

[diego_charles]

Hi Adrian,

Thank you for your patience,

Regarding chapter 5,  two inches is the limit for each branch stub.

Stub lengths are also included in the data bus length. The value for termination resistors depends on the impedance of the traces and since they are not required on all cases, the application note does not recommend an specific value. A calculation of their value needs to be performed.

 Typically, only high speed signals like  DATA  require a termination resistors.

Additionally,   you could take into account the following advice made by one of our colleagues on the post:  Impedance Control EMC Signals LPC4370 . The frequency of the SDRAM data signals could be taken into account , for example a SRAM with 120 MHz could not be consider as  high speed, however proper impedance match have to be done to avoid issues.

Regards,

Diego.