LPC51U68 ADC maximum performance

[bonsani]

Hi

Referring to the LPC51U68 datasheet, it is said to have ADC 5MSPS, but it actually comes out to about 200KSPS. Based on 2 channels
Is there an example code to refer to?

[xiangjun_rong]

Hi,

As the following screenshot, the ADC clock can reach up to 80mhz, one ADC conversion needs 15 clock cycles, so the ADC sampling rate can be 80Mhz/15=5MSPS.

If you want to get maximum 5MSPS, you can not use the interrupt mode, because the LPC51U68 interrupt rate can not reach up to 5mhz.

You can use DMA to transfer the ADC result if the ADC conversion rate is up to 5MHz.

Hope it is helpful

BR

XiangJun Rong

[bonsani]

The ADC DMA example included in SDK 2.8.2 does not work until 5MSPS. DMA interrupt occurs.

[xiangjun_rong]

Hi,

The answer is yes, in burst mode, the ADC will continue to sample one by one, so in burst mode, you can not control the ADC conversion rate.

In Fig 79 ADC block diagram, the SCT0 output 7 can trigger ADC, if you want to control the ADC sampling frequency, you have to disable the burst mode, use the hardware triggering mode, the hardware triggering source is SCT0 output 7, so the SCT0 can define the ADC conversion rate. But you have to develop code for the SCT0 output 7 so that it can output PWM signal to trigger ADC.

The SDK has both SCT and ADC code

Hope it can help you

BR

XiangJun Rong

[xiangjun_rong · Accepted solution]

Hi,

I just modified the lpc_adc_dma with burst mode so that you can sample ADC  channel multiple times.

It appears working.

BR

XiangJun Rong

[bonsani]

Example checked.
The example seems to be 100*50000 for 5MSPS.
It works fine.
The problem will not be debugged if you set it to 10 or 1 in SAMPLENUM 100.
Increasing SAMPLENUM causes memory problems
I'll take that into consideration. Thank you.