LPC43xx and SDRAM (EMC) at 204 MHz?

[zzzmqp]

Hello,

did anyone have success using the LPC43xx at 204 MHz with SDRAM at the EMC running at full 204 MHz without clock divider? If so, which SDRAM chip?

Thanks!

[zzzmqp]

Thank you, bernhardfink‌.

As I use the BGA256 package and a Flash part (LPC4337 / LPC4357), it boils down to:

• Max. specified EMC interface frequency is 120 MHz
• Overclocking the EMC might be possible up to 144 MHz at my own risk with serial resistors in the data lines

I won't consider overclocking the MCU, so my options seem to be:

1. MCU at 204 MHz and EMC at 102 MHz (with Divider)
2. MCU and EMC at up to 144 MHz (at my own risk) (without Divider)

Correct? In both cases, what is the recommended clock signal/configuration when using the LPC4337 / LPC4357?

Thanks again!

[bernhardfink · Accepted solution]

For the flash parts you can use any of the CLKx pins for the SDRAM clock. The CLK2 signal provides a fraction of a nanosecond more margin, which might be relevant for the divider configuration. 

It may sound weird, but at the clock line please foresee a pad for a capacitor to GND (close to the SDRAM), which would allow to assemble a small capacitor in the range of 1 ... 10pF. The background here is, that with this capacitor you can stretch the edge of the clock a little bit to a later point in time and this will give another fraction of a nanosecond  more margin in the setup/hold timing. The EMC clock divider is for some reason not perfectly symmetric, so the edge in the middle of a clock cycle is in fact not in the middle. That's the reason for a small loss in setup/hold time margin.

But as said, this applies to the flashless parts, on the flash parts the ratio under bad condition might be at 55:45 compared to the flashless parts where it can be 70:30.

For the PCB design you might think that the shorter the track for the clock line is, the better. Wrong! Make it a little bit longer and you wind for the setup/hold time margin. So don't make it shorter that the address/data lines, maybe a little bit longer.

Regards,

NXP Support Team.

[soledad]

Hi,

According the AN11508 http://www.nxp.com/documents/application_note/AN11508.pdf 

"The key to running the EMC at full speed is to use EMC_CLK01 (CLK0 pin with SFSCLK0 = function 5) and EMC_CLK23 (CLK2 pin with SFSCLK2 = function 5) for the four byte lane feedback clocks, while using EMC_CLK1 (CLK1 pin) and / or EMC_CLK2 (CLK3 pin) to drive the SDRAM clocks. LPC18/43xx pins CLK0/2 remain floating or connected to short PCB traces for access test points and therefore have immediate full swing signal at the feedback clock receiver input. Since CLK1 and CLK3 are not being used as feedback clocks their length may exceed the 6” restriction without affecting the feedback clocks for capturing SDRAM read data."

Please check the last replay from the next thread:

How to get the SDRAM running with 204 MHZ on the LPC4300 Hitex board | www.LPCware.com 

Have a great day,
Sol

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[zzzmqp]

Great, thank you Sol. You actually already answered the question I would have asked next... (clock configuration)

On my current dev board, EMC_CLK0 is wired to drive the SDRAM clock, so I can't change to the AN11508 recommended clock configuration until we design our own board (where EMC_CLK2 will drive the SDRAM clock).

Are there any specific SDRAM chips that are confirmed to work with this setup at 204 MHz? We need 32+MB (256Mb+) at 204+ MHz but are otherwise flexible when it comes to selecting the chip.

Thanks again for confirming...

[bernhardfink]

The EMC interface is specified for a maximum operating frequency of 120MHz. This limitation is mainly caused by the electrical performance of the pads and the pins. If you go beyond 120MHz the shape of the signals will turn from square to sinus, finally this will result in wrong interpretations of what is a 0 and a 1.

You can overclock the interface with lets say 132MHz or 144MHz without clock divider on your own risk, it should work.

I would recommend serial resistors in the data lines for that, in order to reduce overshoting of the signals from the SDRAM to the MCU. If you use CLK0 or CLK2 for that is a don't care, this might play a role when you work with the clock divider. In addition this problem exists on the flashless devices (e.g. LPC4330 and LPC4350) but not on the flash parts (e.g LPC4337 and LPC4357).

If you want to go for SDRAM performance, you also need to work with the BGA256 package, the LQFP packages have a problem with higher speed on the EMC.

As a matter of fact the LPC4300 will not work with 204MHz on the EMC SDRAM i/f, you need to add the clock divider.

Overclocking the MCU with e.g. 216MHz or 228MHz is on your own risk. If you make a good PCB with a perfect ground and power plane this might work. I recommend some sort of cooling for the MCU to avoid permanent high die temperature. 

Regards,

NXP Support Team

[brendonslade]

The link above takes you to lpcware.com but the content was imported to this community site:

https://community.nxp.com/message/759434