Hello Lee,
Please check the below feedback from internal team:
1. The D0-D31 and DQM0-3 signals need to be connected with certain order. These signals will affect the bit order of data which have been read or written. And these signals focus on each word to operate.
2. According to the EMC documentation the controller always accesses the SDRAM in bursts of four words. this means: to be used with the EMC, the SDRAM must be configured for a 128-bit sequential burst .
As long as the address first word address was given by processor, then SDRAM will add the address in the following three words internally. thus 128-bit data can be operated by sequential burst mode.
for example:
For a single 16-bit external SDRAM chip set the burst length to 8. For a single 32-bit SDRAM chip set the burst length to 4.
3.there is a AN11508 in the NXP website which explains the details about SDRAM interface to LPC18xx/43xx EMC.
it also explains the suggested signal connected method.
Hope it helps!
Best regards,
Felipe
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