LPC43xx PLL Phase Synchronization?

[rulamp]

Hello,

In the LPC4370 Datasheet, section 7.23.3, pg 81, it's stated that "All branch clocks are outputs of one of two Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase."

This makes sense. My question is about the phase synchronicity in the upstream steps of the clock generation and distribution.

Assume the oscillator is shared between all PLLs.
Questions:
1) Assuming the frequencies are multiples of each other, will the PLL outputs be in phase? (I assume there is no guarantee, but who knows.)
2) Will the phase of base clocks be affected when being routed through the dividers? For example. PLL0 -> DIVA(4) -> DIVE(200)->CLKOUT. Will CLKOUT and PLL0 be in phase?
  2a) What if we have two clocks?
    PLL0 -> DIVA(4) -> DIVE(200)->CLKOUT
    PLL0 -> DIVA(4) -> BASE_M4_CLK
    Will BASE_M4_CLK and CLKOUT be in phase?

Thanks!

[xiangjun_rong · Accepted solution]

Hi,

Q1) Assuming the frequencies are multiples of each other, will the PLL outputs be in phase? (I assume there is no guarantee, but who knows.)

The following figure is the clock block diagram for LPC437x, it has three PLL modules PLL0(USB0), PLL0(Audio), PLL1, assume that PLL0(Audio), PLL1 multiply the same clock source from XTAL1/XTAL2 crystal and the same pre-divider, post-divider and the multiplier, we can NOT guarantee that the PLL0(Audio) and PLL1 output clock is phase synchronicity, but can guarantee they have the same clock frequency, because the PLL is a self-regulated system.

Q2) Will the phase of base clocks be affected when being routed through the dividers? For example. PLL0 -> DIVA(4) -> DIVE(200)->CLKOUT. Will CLKOUT and PLL0 be in phase?
2a) What if we have two clocks?
PLL0 -> DIVA(4) -> DIVE(200)->CLKOUT
PLL0 -> DIVA(4) -> BASE_M4_CLK
Will BASE_M4_CLK and CLKOUT be in phase?

>>>>Because of delay of gate, even if the BASE_M4_CLK and CLKOUT has the same output clock frequency and from the same clock source, the BASE_M4_CLK and CLKOUT can not guarantee to be in phase.

Hope it can help you

BR

XiangJun Rong

[rulamp]

Great! Thanks so much for the clarification!