LPC43S20 - using AES 128 with code size larger than internal SRAM

[lpcware]

Content originally posted in LPCWare by rsbogdan on Fri Nov 13 14:21:12 MST 2015
We currently use the LPC4337 and load code from the external flash using the 256-bit decryption in firmware.

To move to a Flashless part for cost savings, we will need to use the the LPC43S30 AES 128-bit engine version to keep the Ethernet interface. (LPC43S20 seems to have better availability, but we can't use it)

The LPC43S30 has only 256kB SRAM internal. Our  overall code +  data memory size exceeds this, but I might assume that the AES engine can manage partial code blocks in SRAM (cache-style) ?
Is it true that we can have an internal SRAM size smaller than our executable and we would just have wait states for code misses while (it's) loading alternate 128-bit blocks ?

I can't find this in the AES functional description.

[lpcware]

Content originally posted in LPCWare by vtw.433e on Fri Nov 13 15:05:29 MST 2015
That is NOT correct. It is your responsibility for managing copying your application into internal RAM. None of the Cortex-M class devices support virtual memory (paging etc).