//Chip_I2S_RxConfig//Base audio clock and Master. Fig 160 User Manual Rev 2.1 temp=LPC_CREG->CREG6; LPC_CREG->CREG6 |= (1<<13);//CREG6[13]=1; RX sourcing base_audio_clock temp = LPC_I2S0->DAI & (~(I2S_DAI_WORDWIDTH_MASK | I2S_DAI_MONO | I2S_DAI_SLAVE | I2S_DAI_WS_HALFPERIOD_MASK)); temp |= I2S_WORDWIDTH_32; temp |= I2S_STEREO; temp |= I2S_MASTER_MODE; temp |= I2S_DAI_WS_HALFPERIOD(31);//bits-1 LPC_I2S0->DAI = temp; LPC_I2S0->RXMODE = I2S_RXMODE_CLKSEL(1);//01=BASE AUDIO CLOCK LPC_I2S0->RXBITRATE = 3; //LPC_I2S0->RXRATE = yDiv | (xDiv << 8); //Chip_I2S_TxConfig // 4-wire SLAVE of RX. Fig 152 User Manual Rev 2.1 temp = LPC_I2S0->DAO & (~(I2S_DAO_WORDWIDTH_MASK | I2S_DAO_MONO | I2S_DAO_SLAVE | I2S_DAO_WS_HALFPERIOD_MASK)); temp |= I2S_WORDWIDTH_32; temp |= I2S_STEREO; temp |= I2S_SLAVE_MODE;//I2S_MASTER_MODE; temp |= I2S_DAO_WS_HALFPERIOD(31); LPC_I2S0->DAO = temp; //LPC_I2S0->TXMODE = I2S_TXMODE_CLKSEL(0);//0x0 = Tx fractional rate divider. Select the TX fractional rate divider clock output as the source LPC_I2S0->TXMODE |= I2S_RXMODE_4PIN_ENABLE; LPC_I2S0->TXBITRATE = 3; //pI2S->TXRATE = yDiv | (xDiv << 8); |