Reversing bits in SGPIO output

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Reversing bits in SGPIO output

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NXP Employee
NXP Employee
Content originally posted in LPCWare by JohnR on Mon Sep 17 06:08:30 MST 2012
Based on AN11201.pdf as mentioned in an earlier post, I am reading the outuput of a SPI ADC connected to the SGPIO input of a Diolan 4350 board.

With M4 receiving the data, I can use __RBIT to get the endianness correct, but I want to use M0 to collect the data, leaving M4 for data processing etc. For some reason __RBIT is not implemented for M0 and I have to do the conversion in software which is really slowing up the system.

Is there any way in the SGPIO system of reversing the bit output from the REG or REG_SS registers, I have looked at the schematic in Figure 32 of the manual and there does not seem any easy way of doing this?

Any help would be appreciated again,

John.
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NXP Employee
NXP Employee
Content originally posted in LPCWare by JohnR on Mon Sep 17 08:55:56 MST 2012
Thanks again for the reply.

Yes, I have looked and tested a number of software reversal methods from the Web but, of course, they work but are all much slower than the M3's (1 cycle) __RBIT macro.

It is strange that they would implement the other three reversal methods but not __RBIT.

John.

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NXP Employee
NXP Employee
Content originally posted in LPCWare by starblue on Mon Sep 17 07:02:49 MST 2012
As far as I understand you are out of luck and there is no way to reverse the bit order in the SGPIO.

The User Manual agrees (SGPIO General Description):

– The bit order is optimized for MSB first. Interfaces that require LSB first should use
  a software instruction (RBIT) to reverse the bit order (not supported by the ARM Cortex-M0).

BTW, this is the wrong way around, since you shift the bits into the MSB, the first bit ends up as the LSB once you are done.

Have you tried all the tricks for reversing the bit order in a fast way?
(Search for "bit twiddling hacks".)
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