LPC4353 Timer Clock Source (PCLK)

[M_H]

Hi all, 

I am trying to configure LPC_TIMER1 on the LPC4353, I can't seem to figure out where the PCLK comes from. 

This is the initialisation code used for the timer:

void timer__init() {
	Chip_TIMER_Init(LPC_TIMER1);
	uint32_t clocks_per_second = Chip_Clock_GetRate(CLK_MX_TIMER1);
	uint32_t clocks_per_10ms = clocks_per_second / 100;
	Chip_TIMER_Reset(LPC_TIMER1);
	Chip_TIMER_PrescaleSet(LPC_TIMER1, 0);
	Chip_TIMER_SetMatch(LPC_TIMER1, 1, clocks_per_10ms);
	Chip_TIMER_MatchEnableInt(LPC_TIMER1, 1);
	Chip_TIMER_ResetOnMatchEnable(LPC_TIMER1, 1);
	Chip_TIMER_StopOnMatchEnable(LPC_TIMER1, 1);
	NVIC_SetPriority(TIMER1_IRQn, 2);
	NVIC_ClearPendingIRQ(TIMER1_IRQn);
	NVIC_EnableIRQ(TIMER1_IRQn);
	Chip_TIMER_Enable(LPC_TIMER1);
}

Chip_Clock_GetRate should return the frequency of PCLK used by the timer to increment the count, however using this to setup the match value does not lead to the expected delay. 

Timing the actual delay and comparing this to the expected delay I found the timer seems to be getting incremented 17 times slower than it should be.

The variable clocks_per_second indicates the PCLK should be running at a frequency of 204 MHz, but the timer actual gets incremented as if a 12 MHz signal is used. (204/17 = 12). 

The user manual isn't really clear about how PCLK is derived either. I assume PCLK and CLK_MX_TIMER1 are essentially the same, and looking at Table 155. CCU1 branch clocks would suggest that CLK_MX_TIMER1 is a branch clock generated by clock control unit 1 from BASE_M4_CLK. The CCU configuration registers only allow enabled/disabling the clock, AHB, and wake-up. No scaling options.

CLK_BASE_MX is setup to come from CLKIN_MAINPLL which is setup to run at a frequency of 204 MHz.

Any help would be much appreciated. 

[Alice_Yang]

Hello,

How do you know the below?

"Timing the actual delay and comparing this to the expected delay I found the timer seems to be getting incremented 17 times slower than it should be.

The variable clocks_per_second indicates the PCLK should be running at a frequency of 204 MHz, but the timer actual gets incremented as if a 12 MHz signal is used. (204/17 = 12). 

BR

Alice

[M_H]

Hi Alice, 

After setting a GPO to be toggled directly in the timer interrupt, I found the timer was actually behaving correctly. 

Please could you remove this post?