Hi @KumarBax
EMCStaticConfig0 = 0x81 configures the static memory interface as 16-bit.
With EMCStaticWaitRd0 = 4 and EMCStaticWaitOen0 = 0, the nominal read interval is five CCLK periods. At 51.6 MHz, this corresponds to approximately:
5 × 19.38 ns ≈ 96.9 ns
The measured OE-low interval of approximately 193 ns is close to ten CCLK periods. One possible explanation is that the measured interval covers more than one external memory transfer. For example, if the processor performs a 32-bit read through the 16-bit EMC interface, two 16-bit transfers would be required, resulting in approximately:
2 × 96.9 ns ≈ 193.8 ns
However, the OE waveform alone is not sufficient to confirm this.
Could you please check the instruction/access width that generated this waveform? As a further verification, you could compare explicit 16-bit and 32-bit reads while monitoring OE, CS, and the address lines.
BR
Harry
