Hi,
I've found following updated notes about PLL1 settings in the latest LPC18xx User Manual.
However, our old products did not deal with this.
12.6.5.2 PLL1 control register
Table 123. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description
:
[1] When the PLL1 is enabled, set the AUTOBLOCK bit in the PLL1_CTRL register to 1. This bit
re-synchronizes the clock output during frequency changes that prevents glitches when switching clock
frequencies.
I changed the frequency of PLL 1 as shown below, but will glitch occur?
And, what happens to the CPU when glitch occurs?
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_IRC, true, false);
Chip_Clock_EnableCrystal();
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, 12000000, 180000000, 180000000); // note: PLL1 divide by 2
while(!Chip_Clock_MainPLLLocked());
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
for(int delay=0; delay<= 1240*10; delay++);// Wait 50 us
LPC_CGU->PLL1_CTRL |= (1 << 7) ; /* DIRECT 90MHz -> 180MHz */