Content originally posted in LPCWare by JTR298 on Tue Feb 17 16:53:38 MST 2015
Hello,
I recently purchased a KEIL MCB1800 evaluation board and built the Ethernet demonstration from the Keil example projects in IAR 7.20.2.7431. The ethernet driver provided in the example, for that board, works correctly and the EMAC initializes, Ethernet packets are received, all is well. I feel I have a decent understanding of the process.
However, when following a very similar process on my own LPC1857 board, outlined below, the SWR bit of the DMA_BUS_MODE register (user manual page 720) never reads a zero after resetting - it reads '1' before I initialize anything, and it remains stuck at '1' apparently regardless of what I'm doing. The manual states that you must wait for SWR to clear before programming any core registers. My SCU pinmuxes are setup correctly, and I'm receiving a 50MHz input to the 1857 on the EREFCLK pin (P1_19 in my case, set to E_REF_CLK, page 318 user manual). When I try to go on initializing my PHY chip (Micrel KSZ8081RNA), the E_MDC output (PC_1 Mode 3, page 322) doesn't have a clock output on it, so I know the peripheral is stalling. My goal is simply to initialize the EMAC correctly, nothing more, so I can then initialize my PHY chip and resume development.
My current initialization given the above:
LPC_CREG->CREG6 |= RMII_SELECT; //set RMII mode for EMAC
LPC_CCU1->CLK_M3_ETHERNET_CFG = 0x07; //RUN, AUTO enable, WAKEUP enable - should start the peripheral clock?
LPC_RGU->RESET_CTRL0 = (1 << 22); //22 is the bit position of ethernet reset, reset EMAC in RGU
while (1) {
if(LPC_RGU->RESET_ACTIVE_STATUS0 & (1<<22) ) //wait for reset status to go away, normally does in one IRC clock cycle, just like manual states
break;
}
LPC_ETHERNET->DMA_BUS_MODE |= 0x01; //set the SWR bit to reset the peripheral
vTaskDelay(1); //1mS delay, doesn't matter if we do 500uS, 1mS, 10mS... SWR bit never resets
temp = LPC_ETHERNET->DMA_BUS_MODE; //always reads 0x00020101 in my case, the SWR bit position is always 1
**further init to follow, but above should reset EMAC correctly, unless I'm missing something**
The manual states "The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion." How do I check this? I've verified that I have a 50MHz input clock on E_REF_CLK, and the value of LPC_RGU->RESET_STATUS1 (page 198 manual) all '01's except for ETHERNET_RST which is '11' - this tells me that the EMAC received the RGU reset. Is there any setup step or input condition that I'm missing regarding initializing the EMAC peripheral? Thanks in advance, and I'll be checking this regularly if any more information is needed.
