DAC Pin allocation for 1857

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DAC Pin allocation for 1857

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by LRWEng on Wed Feb 04 15:06:06 MST 2015
I'm doing pin allocation for an 1857 design. There is one DAC and apparently 4 choices of pins for it to come out.

General notes say that P4.3 and P4.4 and PC.3 are multi-func port pins for ADCX-0 and the DAC. It is also mentioned as sharing a DEDICATED ADCX-0 pin (E3) in Table3 of the spec
sheet under "ADC Pin Selection".

I'm aware of preconditioning the pin function for analog with SFS regs, and then selecting the DAC function with a bit in ENAIO2 register. The note for that register mentions ONLY P4.4.

Question is -- when that bit in ENAIO2 is set to enable DAC -- does it come shooting out on any of these other pins? There is no selection I can find in the ADC regs that defers pins
to the DAC function.. Are there ALTERNATE pins for DAC other than P4.4 -- or should I ignore all those notes about "sharing with ADCX-0 ???
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by LRWEng on Fri Feb 13 11:55:21 MST 2015
Hello;;

I think I'm clear on how to enable the DAC function and make it work. My issue is with the ambiguities in the Spec Sheet and User Manual for this part describing which PINS and what conditions the DAC signal appears on particular pins. (BGA256)

The ENAIO1 and ENAIO2 registers are part of the SCU. And ENAIO2 specifically

15.4.8 Analog function select register
For pins which have digital and analog functions, this register selects the analog DAC and
band gap function over any of the possible digital functions.
In addition, the DAC function is pinned out on a dedicated analog pin which is not affected
by this register.
The following pins are controlled by the ENAIO2 register:
  -- refers to PIN4.4 where setting this bit Overrides the ADC function for that particular pin. The "dedicated" pin referred to in the quote above (E3) ---- is NOT truly dedicated to the DAC. It is shared with ADC. So does setting this bit in ENAIO2 bring DAC out on MULTIPLE PINS??

In the question above -- I referred to other pins which were described as possible DAC output pins. But that bit in ENAIO2 is the ONLY place where there seems to be a routing choice given.. See the original question for pins mentioned as possible DAC outputs.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by embd02161991 on Fri Feb 06 16:30:25 MST 2015
Hi,

The D/A Control register (CTRL - address 0x400E 1004) bit description has a DMA_ENA bit that enables DAC and DMA.

When the DMA_ENA bit is cleared (default state after reset), DAC DMA requests are blocked and the DAC output is disabled.
You can find the DAC example in LPCOpen package :
http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc18xx-packages-0

Thanks
NXP Technical Support
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