Content originally posted in LPCWare by wmues on Thu Mar 26 06:03:51 MST 2015
A NAND-Flash is using
- 8 Data bits
- 1 /RD line
- 1 /WR line
- 1 Ready/Busy Line
- 1 Chip Select Line
- 2 ALE/CLE Command Lines
The ALE/CLE Command Lines will be connected to 2 address lines of the CPU. I would leave A0 and A1 open (so you can do a fast 32bit IO to read/write 4 bytes at once) and connect A2 and A3 to ALE/CLE.
So the address window into the CPU memory map is very small.
If you need at least 8 GB of NAND, please check how long the duration of the initial start up is. This can be very long, if all blocks of NAND must be read once at startup time. And remember that you must do the ECC calculation in software, which will limit the read spead. Therefore, performance will be a lot lower than EMMC/SD.
regards
Wolfgang