EMC Clock

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EMC Clock

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Marc Crandall on Mon Aug 15 14:38:52 MST 2011
Hello,

I'm trying to confirm the setting of the LPC1788 EMC Clock.

Basically I am seeing conflicting information in the tools and I'm not 100% sure about the wording of the user manual.

The attached image is the best place to begin my question.

As you see in this image (generated from Keil uVision 4.20) the EMC clock is listed at 39MHz.  The issue is that the EMCClock variable in "system_LPC177x_8x" is actually 78MHz.

The datasheet says that the EMC clock is either the CPU clock or the CPU clock / 2.

However if you look at the diagram in the user manual (Fig 7. Clock generation for the LPC178x/177x) it looks to me that the EMC clock is either sysclk or pll_clk optionally divided by 2.

So I hope this is somewhat clear.  Either the diagram is incorrect, the system_LPC177x_8x.c file is incorrect and/or the wording in the user manual is incorrect.

Can someone clarify this?

Thanks

Marc
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Chinleo on Wed Feb 08 21:29:50 MST 2012
Anybody delt with the problem?
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Marc Crandall on Tue Aug 23 11:10:50 MST 2011
Hi Dave,

I notice this as well.  It looks like it's not multiplying by the MSEL in the PLL1 config.

Neat tool, but it's got to work to be really useful.

usb10185 - Dave explained where this tool is accessed from the UI.  You should check out all the other things in the "Peripherals" menu, a lot of useful stuff.

(Particularly the Fault report lately :))

Marc
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Dave on Tue Aug 23 09:14:45 MST 2011
So, while we're on the subject of Keil's tool, and the schematic of the clocks,
I noticed that when I run my USBLite (modified) program, (which works, by the way), and I have a look at the schematic in the debugger, the clock values look like this:

[img_assist|nid=577|title=|desc=|link=none|align=center|width=800|height=489]








The interesting part is PLL1 is setup as follows:  MSEL = 16, PSEL = 2, USBCLKSEL_Val = 0X00000204.

This tells me that the Keil schematic is wrong for the USB clock also...

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Dave on Tue Aug 23 09:14:24 MST 2011
...
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Dave on Tue Aug 23 09:13:14 MST 2011
...
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Dave on Tue Aug 23 08:22:02 MST 2011
Marc is talking about the debugger.

If you start the debugger [ D(ebug, Start/Stop Debug Session ],

then have a look at the Clock Generation Schematic [ P(eripherals, Clocking and Power Control, Clock Generation Schematic ]

you'll see what he's talking about.

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by usb10185 on Tue Aug 23 06:57:24 MST 2011
Hi Marc,
Where in Keil is this Clock Generation Schematic tool? I can not see it in my setup. Just the configuration wizard.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Dave on Fri Aug 19 09:29:00 MST 2011
mine can...  (lol)
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by nxp21346 on Tue Aug 16 15:16:00 MST 2011
It looks like there is an error in the part User's Manual and the CMSIS Clock setup code. There is a design restriction that the EMC cannot run faster than the CPU clock. To implement this, functionally, the EMC Clock Divider is fed from the CPU clock divider and not from the CPU clock select mux as shown in the User's Manual diagram and the posted diagram from the Keil tool. The behavior of the Keil tool in calculating EMC Clock as CPU Clock / 2 is correct.

Note: The EMC also cannot exceed 80 MHz. This is the reason for the /2 divide option from CPU clock (which can reach 120 MHz)
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