Hello,
The minimum clock cycle time, and therefore the maximum frequency of the SSP in master mode, is limited by the pin electronics to the value given. The SSP block should not be configured to generate a clock faster than that. At and below the maximum frequency, Tcy(clk) = (SSPCLKDIV x (1 + SCR) x CPSDVSR) / fmain. 5The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
Have a great day,
Sol
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