Hi All
I am trying to setup a GPIO Interrupt for rising and falling edge interrupt, this all seems to be working fine. The issue is that the interrupt will not clear when I set the clear register for p2.6.
I have another interrupt on P2.1 which clears correctly. I can step through the code and see the status register clear on p2.1 but when I do the same on p2.6 I see no change. I have tried setting the register directly without using the Chip_GPIOINT_ClearIntStatus() function but still it wont clear. I am at a loss as to why the interrupt will not clear and really just need to get this project moving forwards. Any help would be greatly appreciated.
This is my interrupt handler:
void INTN_Handler(void)
{
UBaseType_t uxSavedInterruptStatus;
NVIC_ClearPendingIRQ(EINT3_IRQn);
uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
BaseType_t xKSZTaskWoken = pdFALSE;
if(Chip_GPIOINT_GetStatusFalling(LPC_GPIOINT,2) & ( 1 << 6 ) ||
Chip_GPIOINT_GetStatusRising(LPC_GPIOINT,2) & ( 1 << 6 ))
{
Chip_GPIOINT_ClearIntStatus(LPC_GPIOINT, 2, (1 << 6));
if( xKbusTaskHandle != NULL )
{
//vTaskNotifyGiveFromISR( xKbusTaskHandle, &xKSZTaskWoken );
//portEND_SWITCHING_ISR( xKSZTaskWoken );
}
}
if(Chip_GPIOINT_GetStatusFalling(LPC_GPIOINT,2) & ( 1 << 1 ))
{
Chip_GPIOINT_ClearIntStatus(LPC_GPIOINT, 2, (1 << 1));
/* Set the INTN flag. */
xMicrelDevice.ul_had_intn_interrupt = 1;
if( xEMACTaskHandle != NULL )
{
//vTaskNotifyGiveFromISR( xEMACTaskHandle, &xKSZTaskWoken );
//portEND_SWITCHING_ISR( xKSZTaskWoken );
}
}
taskEXIT_CRITICAL_FROM_ISR(uxSavedInterruptStatus);
}
and the gpio setup:
NVIC_DisableIRQ(EINT3_IRQn);
//Configure the Kbus clock interrupt pin
Chip_IOCON_PinMux(LPC_IOCON, 2, 6, IOCON_MODE_INACT, IOCON_FUNC0);
Chip_GPIO_SetPinDIRInput(LPC_GPIO, 2, 6);
Chip_GPIOINT_SetIntFalling(LPC_GPIOINT, 2, 1 << 6);
Chip_GPIOINT_SetIntRising(LPC_GPIOINT, 2, 1 << 6);
and the other:
/* Configure GPIO interrupt pin as input */
Chip_GPIO_SetPinDIRInput(LPC_GPIO, 2, 1);
Chip_IOCON_PinMux(LPC_IOCON, 2, KSZ_INTERRUPT_PIN, IOCON_MODE_INACT, IOCON_FUNC0);
/* Configure the GPIO interrupt */
Chip_GPIOINT_SetIntFalling(LPC_GPIOINT, 2, 1 << 1);
Chip_GPIOINT_SetIntRising(LPC_GPIOINT, 2, 0 << 1);
NVIC_DisableIRQ(EINT3_IRQn);
NVIC_SetPriority(EINT3_IRQn, configMAX_LIBRARY_INTERRUPT_PRIORITY/*configMAX_SYSCALL_INTERRUPT_PRIORITY*/);
Just adding an image of the GPIOINT register after trying to clear 2.6.
At the breakpoint the line behind says LPC_GPIOINT->IO2.CLR |= (1<<6); stepping past this I would have expected STATR and STATF to clear the 0x40 bit.
Hi Adam Grant,
Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
The phenomenon is a bit weird, and I'd like to know whether this phenomenon only happens on the P2_6 pin.
In further, please check the voltage state of the P2_6 pin, it may be related to the hardware.
Have a great day,
TIC
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