void gpio_Init(void)
15: {
16:
17: /* Enable AHB clock to the GPIO domain. */
0x000004A4 B510 PUSH {r4,lr}
18: LPC_SYSCON->SYSAHBCLKCTRL |= (0x1UL << 16); /* enable clock for IOCON */
0x000004A6 483E LDR r0,[pc,#248] ; @0x000005A0
0x000004A8 6800 LDR r0,[r0,#0x00]
0x000004AA F4403080 ORR r0,r0,#0x10000
0x000004AE 493D LDR r1,[pc,#244] ; @0x000005A4
0x000004B0 F8C10080 STR r0,[r1,#0x80]
19: LPC_SYSCON->SYSAHBCLKCTRL |= (0x1UL << 6); /* enable clock for GPIO */
20:
21: // Toggle dir
0x000004B4 4608 MOV r0,r1
0x000004B6 F8D00080 LDR r0,[r0,#0x80]
0x000004BA F0400040 ORR r0,r0,#0x40
0x000004BE F8C10080 STR r0,[r1,#0x80]
22: LPC_GPIO1->DIR &= ~(1 << 8); //P1.8 Input
0x000004C2 4839 LDR r0,[pc,#228] ; @0x000005A8
0x000004C4 6800 LDR r0,[r0,#0x00]
0x000004C6 F4207080 BIC r0,r0,#0x100
0x000004CA 4937 LDR r1,[pc,#220] ; @0x000005A8
0x000004CC 6008 STR r0,[r1,#0x00]
23: LPC_GPIO0->DIR |= (1<<3); //P0.3 Output
24:
0x000004CE 4837 LDR r0,[pc,#220] ; @0x000005AC
0x000004D0 6800 LDR r0,[r0,#0x00]
0x000004D2 F0400008 ORR r0,r0,#0x08
0x000004D6 4935 LDR r1,[pc,#212] ; @0x000005AC
0x000004D8 6008 STR r0,[r1,#0x00]
25: LPC_IOCON->PIO1_8 = ((unsigned int) 0x00000000);
26:
0x000004DA F04F0000 MOV r0,#0x00
0x000004DE 4934 LDR r1,[pc,#208] ; @0x000005B0
0x000004E0 6148 STR r0,[r1,#0x14]
27: LPC_GPIO1->IS &= ~(0x1<<8); //sense = Edge
0x000004E2 4831 LDR r0,[pc,#196] ; @0x000005A8
0x000004E4 6840 LDR r0,[r0,#0x04]
0x000004E6 F4207080 BIC r0,r0,#0x100
0x000004EA 492F LDR r1,[pc,#188] ; @0x000005A8
0x000004EC 6048 STR r0,[r1,#0x04]
28: LPC_GPIO1->IBE &= ~(0x1<<8); //single Edge
0x000004EE 4608 MOV r0,r1
0x000004F0 6880 LDR r0,[r0,#0x08]
0x000004F2 F4207080 BIC r0,r0,#0x100
0x000004F6 6088 STR r0,[r1,#0x08]
29: LPC_GPIO1->IEV &= ~(0x1<<8); //aktive Low
0x000004F8 4608 MOV r0,r1
0x000004FA 68C0 LDR r0,[r0,#0x0C]
0x000004FC F4207080 BIC r0,r0,#0x100
0x00000500 60C8 STR r0,[r1,#0x0C]
30: LPC_GPIO1->IE |= (0x1<<8); //interrupt enable
0x00000502 4608 MOV r0,r1
0x00000504 6900 LDR r0,[r0,#0x10]
0x00000506 F4407080 ORR r0,r0,#0x100
0x0000050A 6108 STR r0,[r1,#0x10]
31: NVIC_SetPriority(EINT1_IRQn,3);
32: /* Set up NVIC when I/O pins are configured as external interrupts. */
0x0000050C F04F0037 MOV r0,#0x37
0x00000510 F04F0103 MOV r1,#0x03
1407: if(IRQn < 0) {
0x00000514 2800 CMP r0,#0x00
0x00000516 DA07 BGE 0x00000528
1408: SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1409: else {
0x00000518 074A LSLS r2,r1,#29
0x0000051A 0E14 LSRS r4,r2,#24
0x0000051C 4A25 LDR r2,[pc,#148] ; @0x000005B4
0x0000051E F000030F AND r3,r0,#0x0F
0x00000522 1F1B SUBS r3,r3,#4
0x00000524 54D4 STRB r4,[r2,r3]
0x00000526 E003 B 0x00000530
1410: NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
0x00000528 074A LSLS r2,r1,#29
0x0000052A 0E13 LSRS r3,r2,#24
0x0000052C 4A22 LDR r2,[pc,#136] ; @0x000005B8
0x0000052E 5413 STRB r3,[r2,r0]
1411: }
0x00000530 BF00 NOP
33: NVIC_EnableIRQ(EINT1_IRQn);
0x00000532 2037 MOVS r0,#0x37
1325: NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
0x00000534 F000021F AND r2,r0,#0x1F
0x00000538 2101 MOVS r1,#0x01
0x0000053A 4091 LSLS r1,r1,r2
0x0000053C 0942 LSRS r2,r0,#5
0x0000053E F04F23E0 MOV r3,#0xE000E000
0x00000542 EB030282 ADD r2,r3,r2,LSL #2
0x00000546 F8C21100 STR r1,[r2,#0x100]
1326: }
36: void PIOINT1_IRQHandler(void)
37: {
0x0000054C BD10 POP {r4,pc}
38: if((LPC_GPIO1->RIS & (0x1<<8)) != 0)
39: {
0x0000054E 4816 LDR r0,[pc,#88] ; @0x000005A8
0x00000550 6940 LDR r0,[r0,#0x14]
0x00000552 F4107F80 TST r0,#0x100
0x00000556 D022 BEQ 0x0000059E
40: LPC_GPIO1->IE = 0x000;
0x00000558 2000 MOVS r0,#0x00
0x0000055A 4913 LDR r1,[pc,#76] ; @0x000005A8
0x0000055C 6108 STR r0,[r1,#0x10]
41: LPC_GPIO0->DATA ^= (1 << 3);
0x0000055E 4817 LDR r0,[pc,#92] ; @0x000005BC
0x00000560 6800 LDR r0,[r0,#0x00]
0x00000562 F0800008 EOR r0,r0,#0x08
0x00000566 4915 LDR r1,[pc,#84] ; @0x000005BC
0x00000568 6008 STR r0,[r1,#0x00]
42: while(LPC_GPIO1->RIS & (1<<8))
43: {
0x0000056A E00F B 0x0000058C
44: LPC_GPIO1->IC = (0x1<<8);
0x0000056C F44F7080 MOV r0,#0x100
0x00000570 490D LDR r1,[pc,#52] ; @0x000005A8
0x00000572 61C8 STR r0,[r1,#0x1C]
45: __NOP();
0x00000574 BF00 NOP
46: __NOP();
0x00000576 BF00 NOP
47: __NOP();
0x00000578 BF00 NOP
48: __NOP();
0x0000057A BF00 NOP
49: __NOP();
0x0000057C BF00 NOP
50: __NOP();
0x0000057E BF00 NOP
51: __NOP();
0x00000580 BF00 NOP
52: __NOP();
0x00000582 BF00 NOP
53: __NOP();
0x00000584 BF00 NOP
54: __NOP();
0x00000586 BF00 NOP
55: __NOP();
0x00000588 BF00 NOP
56: __NOP();
57:
58: }
0x0000058A BF00 NOP
42: while(LPC_GPIO1->RIS & (1<<8))
43: {
44: LPC_GPIO1->IC = (0x1<<8);
45: __NOP();
46: __NOP();
47: __NOP();
48: __NOP();
49: __NOP();
50: __NOP();
51: __NOP();
52: __NOP();
53: __NOP();
54: __NOP();
55: __NOP();
56: __NOP();
57:
58: }
0x0000058C 4806 LDR r0,[pc,#24] ; @0x000005A8
0x0000058E 6940 LDR r0,[r0,#0x14]
0x00000590 F4107F80 TST r0,#0x100
0x00000594 D1EA BNE 0x0000056C
59: LPC_GPIO1->IE = 0x100;
60: }
0x00000596 F44F7080 MOV r0,#0x100
0x0000059A 4903 LDR r1,[pc,#12] ; @0x000005A8
0x0000059C 6108 STR r0,[r1,#0x10]
61: }
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