LPC11C14 SPI configuration

[lpcware]

Content originally posted in LPCWare by Detli on Thu Dec 19 07:58:14 MST 2013
Hello,

i have a problem with the spi unit and i hope there is someone who can help me! :-)

I like to read data from an ADC with 24 MHz.
I use the internal RC oszillator with the pll for 48 MHz.
So i adjust the spi registers, but whenn i measure the spi clock with an oscilloscop, i measure only 12 MHz Clock.
Maybe i have a fault in my code?

###################################################

From system_LPC11xx.c :

#define CLOCK_SETUP           1
#define SYSCLK_SETUP          1
#define SYSOSC_SETUP          1
#define SYSOSCCTRL_Val        0x00000000
#define WDTOSC_SETUP          0
#define WDTOSCCTRL_Val        0x00000000
#define SYSPLLCLKSEL_Val      0x00000000
#define SYSPLL_SETUP          1
#define SYSPLLCTRL_Val        0x00000023
#define MAINCLKSEL_Val        0x00000003
#define SYSAHBCLKDIV_Val      0x00000001
#define AHBCLKCTRL_Val        0b0011011111111111111
#define SSP0CLKDIV_Val        0x00000001
#define UARTCLKDIV_Val        0x00000001
#define SSP1CLKDIV_Val        0x00000001

####################################################

From my main.c :

//SPI0
LPC_SYSCON->PRESETCTRL|= 0x01;//Reset De-Assert SPI0
LPC_SYSCON->SSP0CLKDIV|= 0x01;//Clock Divider = 1

//MISO
LPC_GPIO0->DIR&= ~(1<<8);
LPC_IOCON->PIO0_8|= 0x01;
//MOSI
LPC_GPIO0->DIR|= (1<<9);
LPC_IOCON->PIO0_9|= 0x01;
//CLK
LPC_IOCON->SCK_LOC|= 0x02;
LPC_GPIO0->DIR|= (1<<6);
LPC_IOCON->PIO0_6 |= 0x02;
//CS
LPC_GPIO2->DIR|= (1<<8);
LPC_IOCON->PIO2_8|= 0x10;
LPC_GPIO2->DATA|= (1<<8);

//Serial Clock Rate = PCLK / ( CPSDVSR*(SCR+1) ) ; SCR=0 ; PCLK=48MHz ; CPSDVSR=2 ;
//LPC_SSP0->DR = Data Register to write
LPC_SSP0->CPSR|= 0x02;//CPSDVSR = 2
LPC_SSP0->CR0 = 0x00;
LPC_SSP0->CR0|= 0x18f;//16bit Transfer ; SPI Format ; CLK Low between Frames ; SCR = 1

uint8_t i;
for ( i = 0; i < 8; i++ )
{
     spi_data = LPC_SSP0->DR;    //Tab 210 clear the RxFIFO
}

NVIC_EnableIRQ(SSP0_IRQn);    //Tab 442
LPC_SSP0->CR1|= 0x02;//SPI Enable

#############################################################

[lpcware]

Content originally posted in LPCWare by 1234567890 on Mon Dec 23 05:29:41 MST 2013

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Quote: R2D2

If you want to write 2 frames, you shouldn't toggle CS meanwhile...

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Have you tried this?
- CS low
- for-loop
- CS high

[lpcware]

Content originally posted in LPCWare by Detli on Fri Dec 20 12:34:31 MST 2013
Have no one a answer?

[lpcware]

Content originally posted in LPCWare by Detli on Thu Dec 19 23:02:06 MST 2013
First of all, thanks for your help! :-)

I  hope it is a problem of the code. But it is possible, that the SPI Unit takes minimum 1,5 µS before it can receive a new frame?
If its true, than I have a real problem!

At the moment, the sending time for 16 bit  is about 700ns [ (1/24MHz )*16 = 666,67ns ].
Than there is a pause for 800ns before the next receiving starts.
Why is this break so long? I know there must be a little time between the frames, but that should not so long? I have tryed it with the code that was posted yesterday. I found no new knowledge in the example..

Many thanks

[lpcware]

Content originally posted in LPCWare by R2D2 on Thu Dec 19 10:47:08 MST 2013
BTW: There's a SSP sample in NXP_LPCXpresso11C24_2011-01-27.zip.

If you want to write 2 frames, you shouldn't toggle CS meanwhile...

[lpcware]

Content originally posted in LPCWare by Detli on Thu Dec 19 09:45:18 MST 2013
Yes, it works as master!

#####################################################
global:

uint8_t i = 0;
uint16_t Signal[100];

######################################################

main:

for(i=0;i<100;i++)
{
      spi_receive();
}//for

######################################################
void spi_receive()
{
//CS Low
LPC_GPIO2->MASKED_ACCESS[(1<<8)] = 0;

LPC_SSP0->DR = 0xff;//Dummy
while( ( LPC_SSP0->SR&(1<<4) ) ); //Wait until BUSY Bit clear

        //CS High
LPC_GPIO2->MASKED_ACCESS[(1<<8)] = ~0;

Signal = LPC_SSP0->DR;//Read Value
}//spi_receive()

[lpcware]

Content originally posted in LPCWare by R2D2 on Thu Dec 19 09:40:46 MST 2013

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Quote: Detli
I will explain :-)

The time between two 16 bit frames is to long.

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This are frames which are generated from LPC11C14 as master?

Could be useful if you post this part of your code....

[lpcware]

Content originally posted in LPCWare by Detli on Thu Dec 19 09:21:28 MST 2013
I will explain :-)

The time between two 16 bit frames is to long.
When I will receive frames directly behind on another, than the time between them is so long like the receiving time.
The break between them should not exist.

I hope you can understand my problem now.

[lpcware]

Content originally posted in LPCWare by R2D2 on Thu Dec 19 09:15:12 MST 2013

---

Quote: Detli
The time between two receives is to long...

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No idea who receives what here  :quest:

[lpcware]

Content originally posted in LPCWare by Detli on Thu Dec 19 09:03:21 MST 2013
Thank you for the hint and the fast reply!

But I have already changed this to:
 
     LPC_SSP0->CR0 |= 0x8f;

and then, i measured it with my oscilloscop. Here was the fault, the parasitary capacitance of the probe had changed the signal -.-

Thank you ! It works now correctly ! :-)

But there is another problem!

The time between two receives is to long, i can get only 800kHz and not 1,5MHz (24MHz / 16bit).
Maybe you have a solution for this problem?

[lpcware]

Content originally posted in LPCWare by R2D2 on Thu Dec 19 08:10:53 MST 2013

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Quote: Detli
Maybe i have a fault in my code?

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Yes.

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Quote: Detli


//Serial Clock Rate = PCLK / ( CPSDVSR*(SCR+1) ) ; SCR=0 ; PCLK=48MHz ; CPSDVSR=2 ;
//LPC_SSP0->DR = Data Register to write
LPC_SSP0->CPSR|= 0x02;//CPSDVSR = 2
LPC_SSP0->CR0 = 0x00;
LPC_SSP0->CR0|= 0x[color=#f00]1[/color]8f;//16bit Transfer ; SPI Format ; CLK Low between Frames ; SCR = 1

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With SCR= 1  your SPI clock is 48MHz / (2*2) = 12MHz  :)