LPC1114 SSP TX FIFO clear

[lpcware]

Content originally posted in LPCWare by romko on Wed Oct 22 01:41:59 MST 2014
Hi,

I have iplemanted SPI slave device on my LPC1114 processor. My system put data to the SSP TX FIFO on the TXMIS (TX FIFO is at least half empty) interrupt. So it is always "pumping" data to the TX FIFO.
For providing packet integrity I need somehow reset data that already exists in the TX FIFO in case when some error ocured. For now I haven't find better solution than reseting complete SSP peripheral by

 
LPC_SYSCON->PRESETCTRL &= ~(0x01 << 0);
LPC_SYSCON->PRESETCTRL |= (0x01 << 0);

Is the better way to clear SSP TX FIFO ?

[lpcware]

Content originally posted in LPCWare by NXP_Paul on Thu Oct 23 06:20:41 MST 2014
You could configure the pins to standard GPIO pins before implementing the reset.  This would allow you to maintain signal levels on the bus while resetting, then configure back to the SPI pins after the reset.

[lpcware]

Content originally posted in LPCWare by romko on Thu Oct 23 01:50:48 MST 2014
Reseting peripheral is not the best way of handling such problem, becouse I have noticed that peripheral reset influence on the SPI pins levels. As I have several slave devices on the bus when I reset SSP peripheral, it affect to the bus signals and communication with other slaves.
Is the way to reset FIFO without reseting all peripheral and negative impatc the signal levels ?

[lpcware]

Content originally posted in LPCWare by NXP_Paul on Wed Oct 22 09:35:16 MST 2014
Using the PRESETCTRL register is the best way that I am aware of to reset the SSP periperal.

Paul