LPC Syscon Header File Error

[mikenn]

What's up NXP,

I am using IAR IDE Arm 8.50.9 on NXP LPC11E66JBD48. 

I was unable to get USART0 running properly on the receive function, specifically detecting incoming data, breaks etc.  I had the digital glitch filters programmed to reject glitches shorter than a single clock cycle as such:

                LPC_SYSCTL->IOCONCLKDIV[0] = 0x00000001;    /* IOCON glitch filter clock divider. */

                LPC_SYSCTL->IOCONCLKDIV[1] = 0x00000000;    /* IOCON glitch filter clock divider. */

                LPC_SYSCTL->IOCONCLKDIV[2] = 0x00000000;    /* IOCON glitch filter clock divider. */

                LPC_SYSCTL->IOCONCLKDIV[3] = 0x00000000;    /* IOCON glitch filter clock divider. */

                LPC_SYSCTL->IOCONCLKDIV[4] = 0x00000000;    /* IOCON glitch filter clock divider. */

                LPC_SYSCTL->IOCONCLKDIV[5] = 0x00000000;    /* IOCON glitch filter clock divider. */

                LPC_SYSCTL->IOCONCLKDIV[6] = 0x00000000;    /* IOCON glitch filter clock divider. */

                LPC_IOCON->PIO0[18] = 0x08B1;                             /* PIO0_18 pin is bootloader RXD. */

This initialization sets the USART0 receive digital filter to use clock divider 0 but the receive did not work as it should until I turned on divider 6:

                LPC_SYSCTL->IOCONCLKDIV[0] = 0x00000000;    /* IOCON glitch filter clock divider. */

                LPC_SYSCTL->IOCONCLKDIV[1] = 0x00000000;    /* IOCON glitch filter clock divider. */

                LPC_SYSCTL->IOCONCLKDIV[2] = 0x00000000;    /* IOCON glitch filter clock divider. */

                LPC_SYSCTL->IOCONCLKDIV[3] = 0x00000000;    /* IOCON glitch filter clock divider. */

                LPC_SYSCTL->IOCONCLKDIV[4] = 0x00000000;    /* IOCON glitch filter clock divider. */

                LPC_SYSCTL->IOCONCLKDIV[5] = 0x00000000;    /* IOCON glitch filter clock divider. */

                LPC_SYSCTL->IOCONCLKDIV[6] = 0x00000001;    /* IOCON glitch filter clock divider. */

Looking at the NXP User Manual UM10732 19 December 2016 on page 52 you will note NXP assigned the IOCONCLKDIVx registers in reverse order, i.e. IOCONCLKDIV0 is assigned to 0x4004814C and IOCONCLKDIV6 is assigned to 0x40048134.  I believe the author of syscon_11u6x.h header file did not account for this in their declaration.  IAR tech support tells me this header file is NXP property and thus NXP should be notified about fixing it.  This is easy to fix myself in the file but I can see this tripping up others in the future.

Regards,

MikeN

[Alice_Yang]

Hello @mikenn 

Thanks so much for your sharing, I will take a ticket to our internal team. Sorry for the inconvenient to you.

BR

Alice