Content originally posted in LPCWare by wavemed on Thu Mar 22 14:23:09 MST 2012 Hi CarlMle, I've insert a micro wire under the BGA to touch the P2.10 in order to tie it to ground during reset. I had successful and I've unlock both the board erasing flash via UART0. Now I'm going to redesign the board with the P2.10 carried out. In my case the processor has lost the JTAG when the software has write an value on the MPU register before the initialization of the external SDRAM. There are many JTAG lost cases reported, PLL, MPU ecc..
Content originally posted in LPCWare by CarlMle on Thu Mar 22 02:58:35 MST 2012 Hi,
Yeah we built a product with a LPC1788 and also lost JTAG control, after looking at everything else on the board we modified it to access UART0 and used flashmagic to program it. Once it had been flashed via UART0 jtag control returned.
Talking to an NXP FAE this is known about it's annoying that it's not stated in the datasheet.
Content originally posted in LPCWare by wavemed on Mon Mar 19 15:34:24 MST 2012 Hi Kevin, my problem is similar but I've design a my micro board with the LPC1788 in BGA package with external SDRAM and NOR flash, during debug on the first board I've put a MPU command in initialization code, before of stack assigment. after the reset the device has hang. No more JTAG controal. Some time the Jlink or ULINK shows me CoreSight identifier but it does not enter in debug mode, some time it doesn't connect the JTAG completely. On the second board, I've accidentally change the ".ini" section on the linker from internal flash to the sdram and the second board hang too... My problem is that in my design I've not connect the ISP because it is not necessary to my application, and now the P2.10 pin is alone under the BGA. Now I've only an other board before the revision. I'm really frustrated. Is really not a good feature the disconnection of the JTAG when the processor hang. None has tell me that is necessary to carry out the ISP pin! This should be the first raccomandation on the data sheet or user manual! I'm very disappointed, I don't know if I'll continue the design of my product with such processor...
Content originally posted in LPCWare by bourgeois on Tue Feb 07 00:46:45 MST 2012 Thanks for the tip Kevin. I managed to reset the chip! By entering the ISP mode, as described, and with FlashMagic I could do the full chip reset.
After I post my problem, I read, that when experimenting with PLL, one should add a delay before changing the PLL setting, to give time for the JTAG to take over, before executing this part of code.
Content originally posted in LPCWare by wellsk on Mon Feb 06 09:56:50 MST 2012 You should be able to put the chip in ISP mode on reset and prevent the problematic FLASH boot code from executing.
Here's the specific writeup on how to enter ISP mode. There are some better details in the 17xx user manual in the FLASH memory section. The flash boot loader code is executed every time the part is powered on or reset. The loader can execute the ISP command handler or the user application code. A LOW level after reset at pin P2 is considered an external hardware request to start the ISP command handler using UART0 pins P0 (U0_TXD) and P0 (U0_RXD).