Hi,
The MRT module driving clock is from the AHB clock(Bus clock), for example, if the core clock of LPC54606J512BD100 is 180mhz, the AHB bus clock is also 180MHz, clock cycle time is 1/180MHz=5.55555nS
for 1mS delay, the required counter value is 1mS/5.555555nS=180 000
for 100mS delay, the required counter value is 100ms/5.55555nS=18 000 000, the counter can not reach up to the value because of limited counter bits.
Because the counter is 24 bits, so that counter maximum value is 2**24=16 777 216, so the maximum delay time is 16 777 216/[(180*(10**6)]=93.206mS.
Hope it can help you
BR
XiangJun Rong