Is 5 better than 4 in MAMTIM setting?

[henry_ding]

Our system clock is 72 MHz. Previously, with the value of 3 in MAMTIM setting, we did see data from memory is corrupted. By setting MAMTIM to be 4, the problem has been addressed. But our question is: will the setting of 5 be better? What's the maximum access time LPC23XX allows?

[bernhardfink]

The User's Manual says

"For system clocks of 60 MHz and above, 4CCLK’s are needed."

With 5 wait clocks it would be even more safe, but you slow down flash access and therefore you lose performance.

Regards,

Bernhard.

[carstengroen]

Bernhard,

what does "With 5 wait clocks it would be even more safe" mean ?

What is "more safe" in this regard, does it mean that with 4 wait states we might see errors anyway ??

[bernhardfink · Accepted solution]

Carsten,

you could always work with a maximum number of waitstates on a flash device, it will work, but it's not required.

Required is the number of waitstates specificed for specific system frequencies.

And here the User's Manual is clear, for 60MHz and above (= max 72MHz) the waitstate number needs to be 4 to work reliably.

You can set it to 5 or 6 or 7, it will work, but with significantly less performance.

Regards,

Bernhard.

[henry_ding]

Thanks, Bernhard!

We have additional two follow up questions:

1. We also operate the processor above the recommended 85C operating temperature. The extended temperature range creates some additional shifts in timing that need to be accounted for. We also operate below the -40C recommended operating range. I’ve been curious if there is any wrap around effect that may happen when stalls at higher operating temperatures are prevented by using a higher MAMTIM setting. Does that higher MAMTIM setting somehow cause a problem to creep in at lower operating temperatures?

2. I would like to understand why you claim there is reduced performance from a higher MAMTIM setting. The User’s Manual states that “Simply put, the Memory Accelerator Module (MAM) attempts to have the next ARM instruction that will be needed in its latches in time to prevent CPU fetch stalls.” It seems that if the MAMTIM number is too low (fewer clock cycles allotted for the prefetch operation, the processor stalls and reduces performances.

[bernhardfink]

There are only two settings you can make in the MAM:

1. Operating mode:  register MAMCR
   This is really about the acceleration of ARM instruction, let's call it instruction cache
   
   
2. Flash access timing:  register MAMTIM
   This is purely about raw access timing to flash cells, has nothing to do with the operating mode.
   The description for MAMTIM clearly says "The MAM Timing register determines how many CCLK cycles are used to access the Flash memory". The operating mode is something different.
   In later LPC devices this register is called FLASHTIM

However, both settings will influence the performance. If the instruction cache is disabled or only patrially enabled, the CPU needs to access more often the flash to get instructions. If you increase the wait states in MAMTIM, you simply add breaks in between each access. If you set more wait state cycles than required, then you give away performance.

Regards,

Bernhard.

[carstengroen]

Thanks Bernhard,

it was just the "more safe" that got me worried :smileyhappy: