Hi Kristina,
there is also an appnote for the LPC546xx (AN12026) which gives a few more details on this topic. It's the same 90nm silicon technology as the LPC4300.
I think the point here is the missing series termination in our eval board designs, it's already included in the impedance budget for space and cost saving reasons.
I don't see it as a super critical parameter, an SDRAM frequency of 102MHz or even the maximum allowed 120MHz is not really high speed. Anyway, a wrong impedance match could generate EMV and you run into problems.
One note to the routing: in general it is of course good to make the tracks as short as possible and with the same length. For the frequencies mentioned above the length is also not very critical, but it shouldn't be too far away. Something below 30mm should be ok. But there is another topic which is not clearly mentioned in our documentation. The timing between the CLK and the other SDRAM signals becomes critical at above mentioned frequencies, escpecially when you choose 204MHz for teh core and 102MHz for the SDRAM. Then the CLK signal comes with a bad 1-0-ratio and this limits the margin. So designing the CLK track longer as the other signals gives back some margin. But it must be done consequently, so all signals for example with 20mm length and only the clock line with 30mm.
Alternatively you could foresee a capacitor pad to GND near to the SDRAM, in order to delay the CLK signal with a 3-8pF capacitor.
Regards,
Bernhard.
