I3C - Ninth bit Target returned - End of Data

[martingcavallo]

Hi everyone!

As I already said in other posts, I am working on an I3C driver for the LPC55536 microcontroller.

One question that I have is how to manage the EOD T-Bit returned by the target in the middle of a read transfer.

The MIPI I3C Basic V1.1.1 specification says:

5.1.2.3.4 Ninth Bit of SDR Target Returned (Read) Data as End-of-Data
In I2C, Read from Target has the issue that only the Controller ends the Read, so 1197 the Target has no ability to control the amount of data it returns. In I3C SDR, by contrast, the Target controls the number of data Words it returns; but it also allows the I3C Controller to abort the Read prematurely when necessary.
This mechanism is controlled purely by the ninth (T) Data bit of each SDR Data Word returned by the I3C Target. The ninth bit is returned by the Target in one of three ways, as explained below.
 • The I3C Target returns the ninth bit as 0 (SDA Low) to end the Message:
 • The Target shall set SDA Low on the falling edge of SCL.
 • On the following rising edge of SCL, the Target shall set SDA to High-Z.
 • The I3C Controller shall drive SDA Low on the rising edge of SCL, thereby overlapping with the Target.
 • The I3C Controller then shall issue either a STOP as shown in Figure 150, or a Repeated START as shown in Figure 151 (on the next clock, or one after, per the normal I2C procedure for setting up SDA to issue a Repeated START).

I didn't find any comments in the LLPC5536 RM that indicates that the target sent an EOD T-Bit. Any bit in the MSTATUS or MERRWARN registers are related to this.

Can the MCU detects this? Is there any way to know that the target set the T-Bit to EOD? The MERRWARN register just offers:

• WRABT bit that indicates an error caused by the I2C target NACKing the write data.
• NACK bit indicates and error caused by the target or targets NACKing the last address.

Has anyone any comment?? Thanks in advance!

BR

Martin

[martingcavallo · Accepted solution]

Hi Carlos! How is it going?

Thank you so much for your response. I can confirm that the EOD T-Bit triggers a Complete interrupt, so then I can request to perform a STOP or R-START. I did some tests attempting to retrieve n bytes, but the target set an EOD T-bit before reaching the n-th byte and the Complete interrupt is triggered. I had the idea that the Complete interrupt was triggered when writing the MWDATABE  register when writing and setting RDTERM when reading only. But that was an uncompleted idea hahaha. I tested it mainly by performing some GET CCC that can return variable data length.

On the other hand, It's good to know the I3C versions. I didn't pay attention to that before. Thanks!!!

Have a nice day!

Best Regards,

Martin

[martingcavallo]

I understand that if the I3C Target set the T-Bit to an EOD, the COMPLETE interrupt is triggered. Can anyone confirm that this is correct??

Thanks in advance!

[CarlosGarabito]

Hi @martingcavallo 

On the manual says:

The I3C bus protocol supports:

• In-band interrupts (IBI). These interrupts go from target to controller without extra wires, and the controller knows which

target sent the interrupt.

• Common Command Codes (CCC)

• Dynamic addressing

• Multi-controller/multi-drop

• Hot-Join (HJ)

• I2C compatibility

The I3C peripheral supports all required and most optional features of the MIPI Alliance Specification for I3C, v1.0, except for

ternary data rates (HDR-TSP and HDR-TSL)

From <https://www.nxp.com/docs/en/reference-manual/LPC553xRM.pdf>

So, I don't know about EOD T-Bit that you say, however, NXP sticks to the protocols, so the I3C protocol that is developed by MIPI Aliance, in this micro is using version 1.0, you need to check that part with the MIPI Aliance protocol.

I hope this will help you

Have a good day

Best Regards