Hi Tarun Chaplot,
I already help you to modify the lpcopen code:periph_spi_sm_int, it now can work with 21Mhz, using the SPI FIFO.
The main problem of lpcopen can't reach higher than 12Mhz is:
1. The system clock should configure higher, if you just use 12Mhz, of couse, it can't reach higher than 12Mhz.
So, you can use PLL to get 96MHZ.
Modify points, in the board.h,
#define BOARD_MAINCLOCKRATE (96000000)
If you use different board, both master and slave SPI board should configure the system clock to 96MHZ.
2. Configure the SPI modoule clock base, the async APB clock should also higher than 12Mhz.
The lpcopen just use 12Mhz as the SPI source, so you can't generate higher than 12MH baudrate.
Please add this code in the main:
Chip_Clock_SetAsyncSysconClockSource(SYSCON_ASYNC_SYSPLLOUT);
Then build and test it in the lpcxpresso LPC54102 board, I can get 21Mhz SPI, and the data is correct, this is the test result and the SPI wave.
I also attached my test project for your reference.
Have a great day,
Kerry
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Hi Tarun Chaplot,
I got the root problem why the master can't receive the correct data from slave in 21MHZ.
It's still the clock problem, the logic analyzer tool sampling rate is not enough, the clock rate is measured wrong.
I check it with the oscilloscope again, the defined 21Mhz baud rate, actually , the output spi clock is 24Mhz.
As you know, the LPC54102, the maximum supported bit rate for SPI slave mode is 21Mbit/s.
But the core clock is 96Mhz, if you debug the code, you will find the SPI divier register is 3, the divider is 4.
Divider 4 will cause the SPI clock rate to : 96M/4=24Mhz.
So, it already exceed the maximum supported bit rate for SPI slave mode.
Then the core is 96Mhz, and it is the source for SPI module, then the slave spi max bit rate is : 96MHz/5=19.2Mhz.
So, I configure code:
#define LPCMASTERCLOCKRATE 19000000
It will set the divider register to 4(divider is 4+1=5), the debug data is:
Then I check the clock rate in the oscilloscope, it is 19.2Mhz, just as defined.
The terminal data is:
You can find, if the master clock is in the range of the slave maximum clock, the transfer data is correct.
If you meet the similar problem in the DMA SPI mode, so, please check your clock configuration like me. use the oscilloscope to check the spi rate, whether it is correct.
I don't have the direct DMA SPI code now, I need time to create and debug it. But tomorrow, I will on my Chinese New Year vocation, maybe the DMA SPI project creation will be in Feb.
So, if you don't mind, you can use my code which send you before at first, just modify the spi_sm_int.c, line79:
#define LPCMASTERCLOCKRATE 19000000
Choose the communication clock to 19Mhz.
If you still want to get the 21Mhz, you need to configure the master SPI module clock to 42MHZ, 63Mhz, 84Mhz.
Wish it helps you!
Have a great day,
Kerry
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