Hi,
I am using LPC4367JBD208 Tri Core controller in out product development. So far we are able to use it in proper manner but the problem we entered is the shortage of on ship RAM.
The available on chip RAM is 154KB and and it is further divided with respect to the core allocation. Below is the memory configuration of Flash bank 1 (M4 Core ) and 2 (M0App)
M4 Core MCU Setting here You can see 40KB RAM is used for application
M0App Core MCU Setting. Here 32 KB RAM is used for Application
M0Sub Core MCU Settings. 16KB RAM is used for application
Now in this case the allocated RAM for the respective flash bank 1 and 2 are not sufficient with respect to the application so need more RAM for the code execution. But then is it possible to use External RAM instead of On chip RAM for any one of the Core say M4 Core?
Looking forward for the response.
BR,
Gaurav More
I don't know details about LPC4367, but there are some issues and conditions to consider.
First, external RAM is driven by peripherals and IO lines, which means you need to set this peripheral and lines up before using them. For static use with the linker (and linker script), you need to modify the startup code to initialize it before RAM data are copied.
Second, you will need those interface lines, especially address and data lines. Are those free in your current design ? And does your derivate support expernal RAM at all ?
Third, external RAM is usually only 16 bit wide. This shouldn't be a problem for you though.
Fourth, you might want to check if code execution from ext. RAM is possible (if you need it). This requires an internal connection to the I-bus.
And finally, you might check which core can access which address spaces. At least the M4 core can use it. This will define what purpose you can use it for.
Hi Frank,
Thanks for the reply,
First, external RAM is driven by peripherals and IO lines, which means you need to set this peripheral and lines up before using them. For static use with the linker (and linker script), you need to modify the startup code to initialize it before RAM data are copied.
We are already using the SDRAM and assigning the specific data using __DATA(RAM8) attribute. But now we are planning to use it for entire application code execution.
Regarding the Startup code and linker script implementation, is there any application note with respect to MCU xpresso will be helpful.
Second, you will need those interface lines, especially address and data lines. Are those free in your current design ? And does your derivate support expernal RAM at all ?
We already have interfaced the SDRAM as mentioned above but regarding the device support to use SDRAM as a external RAM instead of on chip RAM , is not yet clear since not able to find as such information regarding the same.
Third, external RAM is usually only 16 bit wide. This shouldn't be a problem for you though.
Yes it is 16bit wide.
Fourth, you might want to check if code execution from ext. RAM is possible (if you need it). This requires an internal connection to the I-bus.
Yes we are looking for the same purpose, but not clear regarding the internal connection to I-Bus.
And finally, you might check which core can access which address spaces. At least the M4 core can use it. This will define what purpose you can use it for
M4 Core and M0App core any one at a time can access the SDRAM. My actual purpose is to evaluate whether we can use external RAM for M4 Core and on chip RAM for M0App core?
please suggest the input for the same. also let me know if you required further more details.
BR,
Gaurav More
> Regarding the Startup code and linker script implementation, is there any application note with respect to MCU xpresso will be helpful.
None that I am aware of. Perhaps NXP staff members know of any.
I know of SDK examples (at least for the LPC54628) for setup and usage. However, all at runtime after the call to main(). Some of my company's projects use a heavily modified startup code, also for initialising external RAM. But the MCU is not even ARM architecture ...
If you don't need initialized data at that point, you can init the RAM later on, and skip this part.
> Yes we are looking for the same purpose, but not clear regarding the internal connection to I-Bus.
The first indication would be an image like this in the datasheet:
The ext. memory peripheral section of the user manual should clarify if your MCU can execute code from SDRAM. As mentioned, I have no experience with the LPC43xx. And because of the 16-bit bus, expect at least reduced performance.
Perhaps the NXP experts can clarify this point.