I do not understand the wording in chapter 47 on how to select JTAG port for MCU debug at power up. How do I select JTAG port from hardware standpoint ? I do not understand how the boundary scan work to select SWD or JTAG for debug port. Please advise. thank you.
The user is able to interface with the debugger through a command window on HyperTerminal. The debugging MCU is then able to control the target via the JTAG port. Our code running on the debugger sends a series of bits to the JTAG interface, which then stores it in the instruction / data registers of the JTAG. prepaidcardstatus.com
Thank you for shedding some light on this; This is very confusing because Chapter 47 makes it sound otherwise (table 1118).
How do ISP_0 and ISP_1 come into play in SWD ? . i.e. how do they affect SWD functionality if SWD is the only option for LPC54xxx.See below:
Hi bob belmont,
Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
Con Verse is right, the LPC54 parts don't support JTAG debug feature.
And the ISP pins won't affect the SWD feature actually.
I disagree, ISP0 and ISP1 pin do affect SWD. As described in 47.6.2:
I use KEIL with ULINK2 on LPCXpresso54S018M via P1 (SWD). If I hold either SW4 (ISP0) or SW3 (ISP1) then power up or reset while keeping the switch pressed, then I can not access the MCU via the debugger. If I do the same experiment with SW2 (ISP2) then I can access the MCU via the debugger.
Thanks for your reply.
The voltage state of ISP pins will affect the boot sequence of LPC MCU, and they usually force the MCU to enter ISP mode. Overall, they're independent with the SWD port.
To provide the fastest possible support, I'd highly recommend you to review the section: Chapter 3: LPC54018JxM Boot ROM for non-secure devices in the UM11155.