Glitch Filter Clock Divide Register Selection problem

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Glitch Filter Clock Divide Register Selection problem

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by mvinger on Sun Jul 21 11:02:24 MST 2013
I am using an LPC812 and LPCXpresso.
I have just attempted to use the Glitch Filters on the inputs and found something fairly odd.
To use IOCONCLKDIV0 I must set the PIO0_x register CLK_DIV to use IOCONCLKDIV6 or I must write the value I wish to use in IOCONCLKDIV6. It seems there is a reversal of the selection/use.

MTV2
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