FTM channel flag not clearing

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FTM channel flag not clearing

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rmaier
Contributor III

Hello,

 

I am having an issue clearing a channel flag for an FTM input capture interrupt. This is on the LPC865M201. The application is glitch filtering out subsequent pulses so that after the initial interrupt, the channel interrupt is disabled for several ms. The problem appears to be that the flag does not clear. So, the interrupt is called accidentally when another ch interrupts. Below is the sample code of what's going on inside the interrupt.

 

if (1 == ((FTM0->CONTROLS[0].CnSC & FTM_CnSC_CHF_MASK) >> FTM_CnSC_CHF_SHIFT))
{
 (void)FTM0->CONTROLS[0].CnSC;		/* Read to clear flag */
 FTM0->CONTROLS[0].CnSC ^= FTM_CnSC_CHF_MASK; /* Clear flag */
 FTM0->CONTROLS[0].CnSC turnoff FTM_CnSC_CHIE_MASK;   //Disable Interrupt
 kl_Intervals[kl_intPointer] = FTM0->CONTROLS[0].CnV + 0xFFFFUL * 
 kl_OverFlowCounter - kl_lastTick;
 kl_Timers[kl_intPointer] = FTM0->CONTROLS[0].CnV;
 kl_intPointer = (kl_intPointer + 1) % 50;
 kl_lastTick = FTM0->CONTROLS[0].CnV;
}

 

 

 

rmaier_0-1695656927911.png

Based on the RM, there are two lines to clear a channel flag:

 

(void)FTM0->CONTROLS[0].CnSC; /* Read to clear flag */
FTM0->CONTROLS[0].CnSC ^= FTM_CnSC_CHF_MASK; /* Clear flag */

 

 

However, stepping through this in debug mode shows that CHF stays at 1. I've tried clearing the flag using the STATUS register to no avail.

What's interesting is that this works fine without glitch filter (i.e. no disabling interrupt). Although, the CHF is still not cleared when debug stepping. Only when the CHIE is disabled do we see false interrupts (CHF not cleared, CHIE = disabled).

Any ideas on what might be going wrong here?

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Alice_Yang
NXP TechSupport
NXP TechSupport

Hello @rmaier 

", the channel interrupt is disabled for several ms. The problem appears to be that the flag does not clear. So, the interrupt is called accidentally when another ch interrupts."

->> Each CHIE control one channel, so for example, disable channel 0 interrupt, channel still can enter interrupt.

And pay attention:

"If another event occurs between the read and write operations, the write operation has no
effect; therefore, CHF remains set indicating an event has occurred."

 

BR

Alice

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rmaier
Contributor III

Thanks for your reply, Alice. How can it be that the interrupt flag is not cleared? Writing the two lines below should clear the flag. This is the problem I am having is that stepping through this in debug mode shows the flag never clearing. While an interrupt is no longer generated, the flag remains set and the code is executed from another interrupt source (while CHF ==1).

Then disabling the interrupt would prevent another flag from being set. That's how I've been used to working with FTM on other NXP MCUs. Did I get something wrong here?

(void)FTM0->CONTROLS[0].CnSC;		/* Read to clear flag */
 FTM0->CONTROLS[0].CnSC ^= FTM_CnSC_CHF_MASK; /* Clear flag */

  Interrupt would be disabled with this line so that no flag can be set.

FTM0->CONTROLS[0].CnSC turnoff FTM_CnSC_CHIE_MASK;   //Disable Interrupt

 

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Alice_Yang
NXP TechSupport
NXP TechSupport

Hello @rmaier 

There is a demo about two channel under SDK, how about first test with it?

Does the issue can reproduce on this demo?

Alice_Yang_0-1696735157880.png

 

BR

Alice

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rmaier
Contributor III

Hello Alice,

I don't think any of the examples address the issue at hand. The twochannel example is regarding PWM. I am using output compare. Disabling the output compare interrupt does not immediately disable the output compare interrupt. Also, clearing the flag does not seem to actually clear the flag.

 

When stepping through in debug. We can see that CHF = 1 for FTM0_CH0. Normally one would expect the following line to then clear the interrupt flag.

(void)FTM0->CONTROLS[0].CnSC;		/* Read to clear flag */
 FTM0->CONTROLS[0].CnSC ^= FTM_CnSC_CHF_MASK; /* Clear flag */

 

However, even after stepping several lines CHF =1 still remains.

This is the problem. Any ideas on what is why this is? None of the examples directly deal with enabling and disabling the interrupts regularly during runtime.

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Alice_Yang
NXP TechSupport
NXP TechSupport

Hello @rmaier 

 

Please send your project to me, I can help to check on my side.

 

BR

Alice

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